Signed-off-by: Jike Song <jike.s...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 147 +++++++++++++++++++++++++++++++++---
drivers/gpu/drm/i915/intel_uncore.c | 3 +
2 files changed, 138 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c3b03f5..ed6f14e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -38,6 +38,7 @@
#include "intel_lrc.h"
#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
+#include "i915_vgt.h"
#include <linux/io-mapping.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
@@ -2915,19 +2916,121 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv,
int val);
#define FORCEWAKE_MEDIA (1 << 1)
#define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
+#define I915_READ8(reg)
\
+({ \
+ u8 __ret = 0; \
+ if (i915.enable_vgt) \
+ vgt_emulate_host_read(reg, &__ret, sizeof(u8), \
+ false, true); \
+ else \
+ __ret = dev_priv->uncore.funcs.mmio_readb(dev_priv, \
+ (reg), true); \
+ __ret; \
+})
+
+#define I915_READ16(reg) \
+({ \
+ u16 __ret = 0; \
+ if (i915.enable_vgt) \
+ vgt_emulate_host_read(reg, &__ret, sizeof(u16), \
+ false, true); \
+ else \
+ __ret = dev_priv->uncore.funcs.mmio_readw(dev_priv, \
+ (reg), true); \
+ __ret; \
+})
+
+#define I915_READ16_NOTRACE(reg) \
+({ \
+ u16 __ret = 0; \
+ if (i915.enable_vgt) \
+ vgt_emulate_host_read(reg, &__ret, sizeof(u16), \
+ false, false); \
+ else \
+ __ret = dev_priv->uncore.funcs.mmio_readw(dev_priv, \
+ (reg), false); \
+ __ret; \
+})
+
+#define I915_READ(reg) \
+({ \
+ u32 __ret = 0; \
+ if (i915.enable_vgt) \
+ vgt_emulate_host_read(reg, &__ret, sizeof(u32), \
+ false, true); \
+ else \
+ __ret = dev_priv->uncore.funcs.mmio_readl(dev_priv, \
+ (reg), true); \
+ __ret; \
+})
+
+#define I915_READ_NOTRACE(reg) \
+({ \
+ u32 __ret = 0; \
+ if (i915.enable_vgt) \
+ vgt_emulate_host_read(reg, &__ret, sizeof(u32), \
+ false, false); \
+ else \
+ __ret = dev_priv->uncore.funcs.mmio_readl(dev_priv, \
+ (reg), false); \
+ __ret; \
+})
+
-#define I915_READ8(reg)
dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
-#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv,
(reg), (val), true)
+#define I915_WRITE8(reg, val) \
+({ \
+ u8 __val = (val); \
+ if (i915.enable_vgt) \
+ vgt_emulate_host_write(reg, &__val, sizeof(u8), \
+ false, true); \
+ else \
+ dev_priv->uncore.funcs.mmio_writeb(dev_priv, \
+ reg, val, true); \
+})
+
+#define I915_WRITE16(reg, val) \
+({ \
+ u16 __val = (val); \
+ if (i915.enable_vgt) \
+ vgt_emulate_host_write(reg, &__val, sizeof(u16), \
+ false, true); \
+ else \
+ dev_priv->uncore.funcs.mmio_writew(dev_priv, \
+ reg, val, true); \
+})
+
+#define I915_WRITE16_NOTRACE(reg, val) \
+({ \
+ u16 __val = (val); \
+ if (i915.enable_vgt) \
+ vgt_emulate_host_write(reg, &__val, sizeof(u16), \
+ false, false); \
+ else \
+ dev_priv->uncore.funcs.mmio_writew(dev_priv, \
+ reg, val, false); \
+})
-#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv,
(reg), true)
-#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv,
(reg), (val), true)
-#define I915_READ16_NOTRACE(reg)
dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
-#define I915_WRITE16_NOTRACE(reg, val)
dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
+#define I915_WRITE(reg, val) \
+({ \
+ u32 __val = (val); \
+ if (i915.enable_vgt) \
+ vgt_emulate_host_write(reg, &__val, sizeof(u32), \
+ false, true); \
+ else \
+ dev_priv->uncore.funcs.mmio_writel(dev_priv, \
+ reg, val, true); \
+})
-#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv,
(reg), true)
-#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv,
(reg), (val), true)
-#define I915_READ_NOTRACE(reg)
dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
-#define I915_WRITE_NOTRACE(reg, val)
dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
+#define I915_WRITE_NOTRACE(reg, val) \
+({ \
+ u32 __val = (val); \
+ if (i915.enable_vgt) \
+ vgt_emulate_host_write(reg, &__val, sizeof(u32), \
+ false, false); \
+ else \
+ dev_priv->uncore.funcs.mmio_writel(dev_priv, \
+ reg, val, false); \
+})
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
* will be implemented using 2 32-bit writes in an arbitrary order with
@@ -2935,8 +3038,28 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv,
int val);
* act upon the intermediate value, possibly leading to corruption and
* machine death. You have been warned.
*/
-#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv,
(reg), (val), true)
-#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv,
(reg), true)
+#define I915_READ64(reg) \
+({ \
+ u64 __ret = 0; \
+ if (i915.enable_vgt) \
+ vgt_emulate_host_read(reg, &__ret, sizeof(u64), \
+ false, true); \
+ else \
+ __ret = dev_priv->uncore.funcs.mmio_readq(dev_priv, \
+ (reg), true); \
+ __ret; \
+})
+
+#define I915_WRITE64(reg, val) \
+({ \
+ u64 __val = (val); \
+ if (i915.enable_vgt) \
+ vgt_emulate_host_write(reg, &__val, sizeof(u64), \
+ false, true); \
+ else \
+ dev_priv->uncore.funcs.mmio_writeq(dev_priv, \
+ reg, val, true); \
+})
#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
u32 upper = I915_READ(upper_reg); \
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 0b0f4f8..774e0fa 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -948,6 +948,9 @@ void intel_uncore_init(struct drm_device *dev)
dev_priv->uncore.funcs.mmio_readq = gen4_read64;
break;
}
+
+ if (i915.enable_vgt)
+ i915_vgt_record_priv(dev_priv);
}
void intel_uncore_fini(struct drm_device *dev)
--
1.9.1
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