On Mon, Aug 11, 2014 at 08:57:36AM +0530, sonika.jin...@intel.com wrote:
> From: Sonika Jindal <sonika.jin...@intel.com>
>
> Renaming the HSW-specific macros for ddi buffer translation slot to denote the
> slot and not the vswing/pre-emph values as they are platform-dependent.
>
> This patch is based on top of the patch series for renaming the DP training
> vswing/pre-emph defines:
> http://lists.freedesktop.org/archives/intel-gfx/2014-August/050407.html
>
> v2: Creating single macro with argument for slot number (Damien)
> v3: Adding macro for num of translation entries (Damien)
>
> Signed-off-by: Sonika Jindal <sonika.jin...@intel.com>
>
> Reviewed-by: Damien Lespiau <damien.lesp...@intel.com>
Aside: If I don't pick up a reviewed patch for a few days please ping me.
It means I've lost it. irc for pings preferred since that's less
embarrassing for me ;-)
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 +---------
> drivers/gpu/drm/i915/intel_ddi.c | 20 +++++---------------
> drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++----------
> 3 files changed, 16 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7a6cc69..7366aac 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5966,15 +5966,7 @@ enum punit_power_well {
> #define DDI_BUF_CTL_B 0x64100
> #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
> #define DDI_BUF_CTL_ENABLE (1<<31)
> -#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
> -#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
> -#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
> -#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
> -#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
> -#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
> -#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
> -#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
> -#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
> +#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
> #define DDI_BUF_EMP_MASK (0xf<<24)
> #define DDI_BUF_PORT_REVERSAL (1<<16)
> #define DDI_BUF_IS_IDLE (1<<7)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index ca1f9a8..c3914b7 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -241,18 +241,6 @@ void intel_prepare_ddi(struct drm_device *dev)
> intel_prepare_ddi_buffers(dev, port);
> }
>
> -static const long hsw_ddi_buf_ctl_values[] = {
> - DDI_BUF_EMP_400MV_0DB_HSW,
> - DDI_BUF_EMP_400MV_3_5DB_HSW,
> - DDI_BUF_EMP_400MV_6DB_HSW,
> - DDI_BUF_EMP_400MV_9_5DB_HSW,
> - DDI_BUF_EMP_600MV_0DB_HSW,
> - DDI_BUF_EMP_600MV_3_5DB_HSW,
> - DDI_BUF_EMP_600MV_6DB_HSW,
> - DDI_BUF_EMP_800MV_0DB_HSW,
> - DDI_BUF_EMP_800MV_3_5DB_HSW
> -};
> -
> static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
> enum port port)
> {
> @@ -276,6 +264,8 @@ static void intel_wait_ddi_buf_idle(struct
> drm_i915_private *dev_priv,
> * DDI A (which is used for eDP)
> */
>
> +#define NUM_FDI_TRANSLATION_ENTRIES (ARRAY_SIZE(hsw_ddi_translations_fdi) /
> 2)
> +
> void hsw_fdi_link_train(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> @@ -312,7 +302,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
>
> /* Start the training iterating through available voltages and emphasis,
> * testing each value twice. */
> - for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
> + for (i = 0; i < NUM_FDI_TRANSLATION_ENTRIES * 2; i++) {
> /* Configure DP_TP_CTL with auto-training */
> I915_WRITE(DP_TP_CTL(PORT_E),
> DP_TP_CTL_FDI_AUTOTRAIN |
> @@ -327,7 +317,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
> I915_WRITE(DDI_BUF_CTL(PORT_E),
> DDI_BUF_CTL_ENABLE |
> ((intel_crtc->config.fdi_lanes - 1) << 1) |
> - hsw_ddi_buf_ctl_values[i / 2]);
> + DDI_BUF_TRANS_SELECT(i / 2));
> POSTING_READ(DDI_BUF_CTL(PORT_E));
>
> udelay(600);
> @@ -402,7 +392,7 @@ void intel_ddi_init_dp_buf_reg(struct intel_encoder
> *encoder)
> enc_to_dig_port(&encoder->base);
>
> intel_dp->DP = intel_dig_port->saved_port_bits |
> - DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
> + DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
> intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
>
> }
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 01f264c..faca3c3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2842,29 +2842,29 @@ intel_hsw_signal_levels(uint8_t train_set)
> DP_TRAIN_PRE_EMPHASIS_MASK);
> switch (signal_levels) {
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
> - return DDI_BUF_EMP_400MV_0DB_HSW;
> + return DDI_BUF_TRANS_SELECT(0);
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
> - return DDI_BUF_EMP_400MV_3_5DB_HSW;
> + return DDI_BUF_TRANS_SELECT(1);
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
> - return DDI_BUF_EMP_400MV_6DB_HSW;
> + return DDI_BUF_TRANS_SELECT(2);
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
> - return DDI_BUF_EMP_400MV_9_5DB_HSW;
> + return DDI_BUF_TRANS_SELECT(3);
>
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
> - return DDI_BUF_EMP_600MV_0DB_HSW;
> + return DDI_BUF_TRANS_SELECT(4);
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
> - return DDI_BUF_EMP_600MV_3_5DB_HSW;
> + return DDI_BUF_TRANS_SELECT(5);
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
> - return DDI_BUF_EMP_600MV_6DB_HSW;
> + return DDI_BUF_TRANS_SELECT(6);
>
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
> - return DDI_BUF_EMP_800MV_0DB_HSW;
> + return DDI_BUF_TRANS_SELECT(7);
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
> - return DDI_BUF_EMP_800MV_3_5DB_HSW;
> + return DDI_BUF_TRANS_SELECT(8);
> default:
> DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
> "0x%x\n", signal_levels);
> - return DDI_BUF_EMP_400MV_0DB_HSW;
> + return DDI_BUF_TRANS_SELECT(0);
> }
> }
>
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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