On Fri, Aug 01, 2014 at 02:04:45AM -0700, Rodrigo Vivi wrote: > With this bit enabled, HW changes the color when compressing frames for > debug purposes. > > ALthough the simple way to enable a single bit is over intel_reg_write, > this value is overwriten on next update_fbc so depending on the workload > it is not possible to set this bit with intel-gpu-tools. So this patch > introduces a persistent way to enable false color over debugfs. > > v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested > v3: (Ville) only do false color for IVB+ since according to spec bit is > MBZ before IVB. > v4: We don't have FBC on valleyview nor on cherryview (Ben) > v5: s/!HAS_PCH_SPLIT/!HAS_FBC (Ville) > > Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> > Reviewed-by: Ben Widawsky <b...@bwidawsk.net> > Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
