On Thu, Jul 03, 2014 at 10:32:38AM +0300, Jani Nikula wrote: > On Thu, 03 Jul 2014, mengdong....@intel.com wrote: > > From: Jani Nikula <jani.nik...@intel.com> > > I wrote this as a quick hack patch to try as an alternative to [1] which > ended up not working on Haswell. Please reassure me that this is going > to be a temporary solution until we get a more generic interface between > the audio and display drivers. I don't much like this, but at least it's > isolated and small. > > I'd like the commit message amended with something like: > > """ > If the display power well has been disabled, the display audio > controller divider values EM4 MVALUE and EM5 NVALUE will have been > lost. The CDCLK frequency is required for reprogramming them. Provide a > private interface for the audio driver to query CDCLK. > > This is a stopgap solution until a more generic interface between audio > and display drivers has been implemented. > """ > > I'd also like to have an additional Reviewed-by from the i915 > side. After that, I'm fine with merging this through alsa.
Sure. Reviewed-by: Damien Lespiau <damien.lesp...@intel.com> -- Damien _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
