From: John Harrison <john.c.harri...@intel.com>
Added various definitions that will be useful for the scheduler in general and
pre-emptive context switching in particular.
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++-
drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 61 ++++++++++++++++++++++++++++++-
3 files changed, 92 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e3295cb..53f6fe5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -584,7 +584,10 @@ struct i915_ctx_hang_stats {
};
/* This must match up with the value previously used for execbuf2.rsvd1. */
-#define DEFAULT_CONTEXT_ID 0
+#define DEFAULT_CONTEXT_ID 0
+/* This must not match any user context */
+#define PREEMPTION_CONTEXT_ID (-1)
+
struct intel_context {
struct kref ref;
int id;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 242df99..cfc918d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -205,6 +205,10 @@
#define MI_GLOBAL_GTT (1<<22)
#define MI_NOOP MI_INSTR(0, 0)
+#define MI_NOOP_WRITE_ID (1<<22)
+#define MI_NOOP_ID_MASK ((1<<22) - 1)
+#define MI_NOOP_MID(id) ((id) & MI_NOOP_ID_MASK)
+#define MI_NOOP_WITH_ID(id) MI_INSTR(0, MI_NOOP_WRITE_ID|MI_NOOP_MID(id))
#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
@@ -222,6 +226,7 @@
#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
#define MI_ARB_ENABLE (1<<0)
#define MI_ARB_DISABLE (0<<0)
+#define MI_ARB_CHECK MI_INSTR(0x05, 0)
#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
#define MI_SUSPEND_FLUSH_EN (1<<0)
@@ -260,6 +265,8 @@
#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
#define MI_SEMAPHORE_SYNC_MASK (3<<16)
#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
+#define MI_CONTEXT_ADDR_MASK ((~0)<<12)
+#define MI_SET_CONTEXT_FLAG_MASK ((1<<12)-1)
#define MI_MM_SPACE_GTT (1<<8)
#define MI_MM_SPACE_PHYSICAL (0<<8)
#define MI_SAVE_EXT_STATE_EN (1<<3)
@@ -270,6 +277,10 @@
#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
#define MI_STORE_DWORD_INDEX_SHIFT 2
+#define MI_STORE_REG_MEM MI_INSTR(0x24, 1)
+#define MI_STORE_REG_MEM_GTT (1 << 22)
+#define MI_STORE_REG_MEM_PREDICATE (1 << 21)
+
/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
* - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
* simply ignores the register load under certain conditions.
@@ -283,7 +294,10 @@
#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
#define MI_FLUSH_DW_STORE_INDEX (1<<21)
#define MI_INVALIDATE_TLB (1<<18)
+#define MI_FLUSH_DW_OP_NONE (0<<14)
#define MI_FLUSH_DW_OP_STOREDW (1<<14)
+#define MI_FLUSH_DW_OP_RSVD (2<<14)
+#define MI_FLUSH_DW_OP_STAMP (3<<14)
#define MI_FLUSH_DW_OP_MASK (3<<14)
#define MI_FLUSH_DW_NOTIFY (1<<8)
#define MI_INVALIDATE_BSD (1<<7)
@@ -1005,6 +1019,19 @@ enum punit_power_well {
#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
#define GEN6_NOSYNC 0
+
+/*
+ * Premption-related registers
+ */
+#define RING_UHPTR(base) ((base)+0x134)
+#define UHPTR_GFX_ADDR_ALIGN (0x7)
+#define UHPTR_VALID (0x1)
+#define RING_PREEMPT_ADDR 0x0214c
+#define PREEMPT_BATCH_LEVEL_MASK (0x3)
+#define BB_PREEMPT_ADDR 0x02148
+#define SBB_PREEMPT_ADDR 0x0213c
+#define RS_PREEMPT_STATUS 0x0215c
+
#define RING_MAX_IDLE(base) ((base)+0x54)
#define RING_HWS_PGA(base) ((base)+0x80)
#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
@@ -5383,7 +5410,8 @@ enum punit_power_well {
#define VLV_SPAREG2H 0xA194
#define GTFIFODBG 0x120000
-#define GT_FIFO_SBDROPERR (1<<6)
+#define GT_FIFO_CPU_ERROR_MASK 0xf
+#define GT_FIFO_SDDROPERR (1<<6)
#define GT_FIFO_BLOBDROPERR (1<<5)
#define GT_FIFO_SB_READ_ABORTERR (1<<4)
#define GT_FIFO_DROPERR (1<<3)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 910c83c..30841ea 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -40,6 +40,12 @@ struct intel_hw_status_page {
#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base),
val)
+#define I915_READ_UHPTR(ring) \
+ I915_READ(RING_UHPTR((ring)->mmio_base))
+#define I915_WRITE_UHPTR(ring, val) \
+ I915_WRITE(RING_UHPTR((ring)->mmio_base), val)
+#define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
+
enum intel_ring_hangcheck_action {
HANGCHECK_IDLE = 0,
HANGCHECK_WAIT,
@@ -280,10 +286,61 @@ intel_write_status_page(struct intel_engine_cs *ring,
* 0x1f: Last written status offset. (GM45)
*
* The area from dword 0x20 to 0x3ff is available for driver usage.
+ *
+ * Note: in general the allocation of these indices is arbitrary, as long
+ * as they're all unique. But a few of them are used with instructions that
+ * have specific alignment requirements, those particular indices must be
+ * chosen carefully to meet those requirements. The list below shows the
+ * currently-known alignment requirements:
+ *
+ * I915_GEM_SCRATCH_INDEX must be EVEN
*/
#define I915_GEM_HWS_INDEX 0x20
-#define I915_GEM_HWS_SCRATCH_INDEX 0x30
-#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX <<
MI_STORE_DWORD_INDEX_SHIFT)
+#define I915_GEM_ACTIVE_SEQNO_INDEX 0x21 /* Executing seqno for TDR only */
+#define I915_GEM_PGFLIP_INDEX 0x22
+#define I915_GEM_BREADCRUMB_INDEX 0x23
+
+#define I915_GEM_HWS_SCRATCH_INDEX 0x24 /* QWord */
+#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX <<
MI_STORE_DWORD_INDEX_SHIFT)
+
+/*
+ * Software (CPU) tracking of batch start/end addresses in the ring
+ */
+#define I915_GEM_BATCH_START_ADDR 0x2e /* Start of batch in ring */
+#define I915_GEM_BATCH_END_ADDR 0x2f /* End of batch in ring
*/
+
+/*
+ * Tracking; these are updated by the GPU at the beginning and/or end of every
batch
+ */
+#define I915_BATCH_DONE_SEQNO 0x30 /* Last completed batch seqno */
+#define I915_BATCH_ACTIVE_SEQNO 0x31 /* Seqno of batch in
progress */
+#define I915_BATCH_ACTIVE_ADDR 0x32 /* Addr of batch cmds in ring */
+#define I915_BATCH_ACTIVE_END 0x33 /* End of batch cmds in ring */
+
+/*
+ * Tracking; these are updated by the GPU at the beginning and/or end of a
preemptive batch
+ */
+#define I915_PREEMPTIVE_DONE_SEQNO 0x34 /* Last completed preemptive
batch seqno */
+#define I915_PREEMPTIVE_ACTIVE_SEQNO 0x35 /* Seqno of preemptive batch in
progress */
+#define I915_PREEMPTIVE_ACTIVE_ADDR 0x36 /* Addr of preemptive batch cmds
in ring */
+#define I915_PREEMPTIVE_ACTIVE_END 0x37 /* End of preemptive batch cmds
in ring */
+
+/*
+ * Preemption; these are used by the GPU to save important registers
+ */
+#define I915_SAVE_PREEMPTED_RING_PTR 0x38 /* HEAD before preemption */
+#define I915_SAVE_PREEMPTED_BB_PTR 0x39 /* BB ptr before preemption */
+#define I915_SAVE_PREEMPTED_SBB_PTR 0x3a /* SBB before preemption */
+#define I915_SAVE_PREEMPTED_UHPTR 0x3b /* UHPTR after preemption */
+#define I915_SAVE_PREEMPTED_HEAD 0x3c /* HEAD after preemption */
+#define I915_SAVE_PREEMPTED_TAIL 0x3d /* TAIL after preemption */
+#define I915_SAVE_PREEMPTED_STATUS 0x3e /* RS preemption status */
+#define I915_SAVE_PREEMPTED_NOPID 0x3f /* Dummy */
+
+/* Range of DWORDs to snapshot in the interrupt handler */
+#define I915_IRQ_SNAP_START I915_GEM_HWS_INDEX
+#define I915_IRQ_SNAP_SPLIT
(I915_SAVE_PREEMPTED_NOPID/4*4+4)
+#define I915_IRQ_SNAP_END
((I915_SAVE_PREEMPTED_NOPID+128)/4*4+4)
void intel_stop_ring_buffer(struct intel_engine_cs *ring);
void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);
--
1.7.9.5
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