From: Oscar Mateo <oscar.ma...@intel.com>
Otherwise, we might receive a new interrupt before we have time to
ack the first one, eventually missing it.
Notice that, before clearing a port-sourced interrupt in the IIR, the
corresponding interrupt source status in the PORT_HOTPLUG_STAT must be
cleared.
Spotted by Bob Beckett <robert.beck...@intel.com>.
Signed-off-by: Oscar Mateo <oscar.ma...@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 59ff177..98009b5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1895,21 +1895,22 @@ static irqreturn_t cherryview_irq_handler(int irq, void
*arg)
if (master_ctl == 0 && iir == 0)
break;
- I915_WRITE(GEN8_MASTER_IRQ, 0);
-
- gen8_gt_irq_handler(dev, dev_priv, master_ctl);
+ ret = IRQ_HANDLED;
- valleyview_pipestat_irq_handler(dev, iir);
+ I915_WRITE(GEN8_MASTER_IRQ, 0);
- /* Consume port. Then clear IIR or we'll miss events */
- i9xx_hpd_irq_handler(dev);
+ if (iir) {
+ /* Consume port. Then clear IIR or we'll miss events */
+ if (iir & I915_DISPLAY_PORT_INTERRUPT)
+ i9xx_hpd_irq_handler(dev);
+ I915_WRITE(VLV_IIR, iir);
+ valleyview_pipestat_irq_handler(dev, iir);
+ }
- I915_WRITE(VLV_IIR, iir);
+ gen8_gt_irq_handler(dev, dev_priv, master_ctl);
I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
POSTING_READ(GEN8_MASTER_IRQ);
-
- ret = IRQ_HANDLED;
}
return ret;
--
1.9.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
