On Tue, May 13, 2014 at 03:05:24PM -0700, Jesse Barnes wrote:
> On Tue, 11 Feb 2014 14:19:03 +0530
> akash.g...@intel.com wrote:
>
> > @@ -810,6 +815,7 @@ static void gen6_ppgtt_insert_entries(struct
> > i915_address_space *vm,
> > pt_vaddr[act_pte] =
> > vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
> > cache_level, true);
> > +
> > if (++act_pte == I915_PPGTT_PT_ENTRIES) {
> > kunmap_atomic(pt_vaddr);
> > pt_vaddr = NULL;
>
> Some extra whitespace here.
>
> Otherwise:
> Reviewed-by: Jesse Barnes <jbar...@virtuousgeek.org>
Hm, looking at the patch again encoding this into the cache_level enum is
fraught with fun. And due to IS_VLV aliasing chv this will blow up on chv
very likely. My old idea was to eventually add a pte_flags param all over
for this stuff with additional bits.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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