On Mon, Jul 13, 2026 at 09:56:26AM -0700, John Harrison wrote: > New transcoder enum values (for CMTG) were recently added which pushed > the maximum transcoder mask beyond 8bits. The patch in question > updated the info structure's u8 to u16 but not any of the functions > that process transcoder masks. So fix those as well. > > Signed-off-by: John Harrison <[email protected]> > Fixes: 789dda6429e0 ("drm/i915/cmtg: Add CMTG transcoder offset in struct > _device_info")
Thanks for this finding. But could you please double check Sashiko? We might have further gaps around this: https://sashiko.dev/#/patchset/20260713165626.2827609-1-John.Harrison%40Igalia.com > Cc: Uma Shankar <[email protected]> > Cc: Animesh Manna <[email protected]> > Cc: Jani Nikula <[email protected]> > Cc: Rodrigo Vivi <[email protected]> > Cc: [email protected] > Cc: [email protected] > --- > drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++---------- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 214454f419e9..38763a6802c5 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -3767,9 +3767,9 @@ static void enabled_joiner_pipes(struct intel_display > *display, > } > } > > -static u8 hsw_panel_transcoders(struct intel_display *display) > +static u16 hsw_panel_transcoders(struct intel_display *display) > { > - u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); > + u16 panel_transcoder_mask = BIT(TRANSCODER_EDP); > > if (DISPLAY_VER(display) >= 11) > panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | > BIT(TRANSCODER_DSI_1); > @@ -3777,13 +3777,13 @@ static u8 hsw_panel_transcoders(struct intel_display > *display) > return panel_transcoder_mask; > } > > -static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) > +static u16 hsw_enabled_transcoders(struct intel_crtc *crtc) > { > struct intel_display *display = to_intel_display(crtc); > - u8 panel_transcoder_mask = hsw_panel_transcoders(display); > + u16 panel_transcoder_mask = hsw_panel_transcoders(display); > enum transcoder cpu_transcoder; > u8 primary_pipe, secondary_pipes; > - u8 enabled_transcoders = 0; > + u16 enabled_transcoders = 0; > > /* > * XXX: Do intel_display_power_get_if_enabled before reading this (for > @@ -3844,18 +3844,18 @@ static u8 hsw_enabled_transcoders(struct intel_crtc > *crtc) > return enabled_transcoders; > } > > -static bool has_edp_transcoders(u8 enabled_transcoders) > +static bool has_edp_transcoders(u16 enabled_transcoders) > { > return enabled_transcoders & BIT(TRANSCODER_EDP); > } > > -static bool has_dsi_transcoders(u8 enabled_transcoders) > +static bool has_dsi_transcoders(u16 enabled_transcoders) > { > return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | > BIT(TRANSCODER_DSI_1)); > } > > -static bool has_pipe_transcoders(u8 enabled_transcoders) > +static bool has_pipe_transcoders(u16 enabled_transcoders) > { > return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | > BIT(TRANSCODER_DSI_0) | > @@ -3863,7 +3863,7 @@ static bool has_pipe_transcoders(u8 enabled_transcoders) > } > > static void assert_enabled_transcoders(struct intel_display *display, > - u8 enabled_transcoders) > + u16 enabled_transcoders) > { > /* Only one type of transcoder please */ > drm_WARN_ON(display->drm, > @@ -5880,7 +5880,7 @@ static int intel_atomic_check_crtcs(struct > intel_atomic_state *state) > } > > static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state > *state, > - u8 transcoders) > + u16 transcoders) > { > const struct intel_crtc_state *new_crtc_state; > struct intel_crtc *crtc; > @@ -6516,7 +6516,7 @@ int intel_atomic_check(struct drm_device *dev, > } > > if (is_trans_port_sync_mode(new_crtc_state)) { > - u8 trans = new_crtc_state->sync_mode_slaves_mask; > + u16 trans = new_crtc_state->sync_mode_slaves_mask; > > if (new_crtc_state->master_transcoder != > INVALID_TRANSCODER) > trans |= BIT(new_crtc_state->master_transcoder); > -- > 2.43.0 >
