On Tue, May 06, 2014 at 02:34:41PM +0100, Damien Lespiau wrote: > On Tue, May 06, 2014 at 02:56:50PM +0300, Jani Nikula wrote: > > From: Paulo Zanoni <paulo.r.zan...@intel.com> > > > > Even if the panel claims it can support 4 lanes, there's the > > possibility that the HW can't, so consider this while selecting the > > max lane count. > > > > Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com> > > Signed-off-by: Jani Nikula <jani.nik...@intel.com> > > Note that we also have an eDP lane count in the VBT we may want to factor > in here as well.
Ah, that's what this series is all about, discard this comment then. -- Damien _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
