> Subject: Re: [PATCH v3 20/26] drm/i915/writeback: Configure WD_STRIDE reg > > On Wed, Mar 25, 2026 at 04:37:38PM +0530, Suraj Kandpal wrote: > > Write to the WD_STRIDE register using the appropriate calculation > > based on the color mode and hactive. > > > > Signed-off-by: Suraj Kandpal <[email protected]> > > --- > > .../gpu/drm/i915/display/intel_writeback.c | 36 +++++++++++++++++++ > > .../drm/i915/display/intel_writeback_reg.h | 1 + > > 2 files changed, 37 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_writeback.c > > b/drivers/gpu/drm/i915/display/intel_writeback.c > > index d3c3716a28a9..e2f7c46015d2 100644 > > --- a/drivers/gpu/drm/i915/display/intel_writeback.c > > +++ b/drivers/gpu/drm/i915/display/intel_writeback.c > > @@ -231,15 +231,51 @@ static int intel_writeback_atomic_check(struct > drm_connector *connector, > > return 0; > > } > > > > +static int > > +get_color_mode_bpp(struct intel_display *display, u32 color_format) { > > + int bpp = 0; > > + > > + switch (color_format) { > > + case DRM_FORMAT_XYUV8888: > > + case DRM_FORMAT_YUYV: > > + case DRM_FORMAT_VYUY: > > + case DRM_FORMAT_XBGR8888: > > + case DRM_FORMAT_XBGR2101010: > > + case DRM_FORMAT_XVYU2101010: > > + bpp = 4; > > + break; > > + default: > > + drm_err(display->drm, "Unsupported format for > writeback\n"); > > + break; > > + } > > + > > + return bpp; > > +} > > + > > static void intel_writeback_capture(struct intel_atomic_state *state, > > struct intel_connector *connector) { > > struct intel_display *display = to_intel_display(connector); > > struct intel_writeback_connector *wb_conn = > > conn_to_intel_writeback_connector(connector); > > + struct drm_connector_state *conn_state = > > + drm_atomic_get_new_connector_state(&state->base, > &connector->base); > > + struct intel_crtc *crtc = intel_crtc_for_pipe(display, wb_conn->pipe); > > + struct intel_crtc_state *crtc_state = > > + intel_atomic_get_new_crtc_state(state, crtc); > > + const struct drm_display_mode *adjusted_mode = > > + &crtc_state->hw.adjusted_mode; > > + struct drm_writeback_job *wb_job = conn_state->writeback_job; > > enum transcoder trans = wb_conn->trans; > > u32 val = 0; > > + int bpp; > > > > + bpp = get_color_mode_bpp(display, wb_job->fb->format->format); > > + val = DIV_ROUND_UP((adjusted_mode->hdisplay * bpp), 64); > > The fb should tell us its stride.
Let me experiment with this. Problem is I remember that the fb's stride value was causing some issue when given as a value. Also I saw this calculation in Bspec which I coded in. Currently I can't tell you what the error exactly since this series was just Made to accommodate the new drm core changes under review to make sure everything still works for us. I will experiment with fb's stride value and get back to you on this. Regards, Suraj Kandpal > > > + intel_de_write(display, WD_STRIDE(trans), WD_STRIDE_VAL(val)); > > + > > + val = 0; > > val |= START_TRIGGER_FRAME | WD_FRAME_NUMBER(wb_conn- > >frame_num); > > intel_de_rmw(display, WD_TRANS_FUNC_CTL(trans), > > START_TRIGGER_FRAME | WD_FRAME_NUMBER_MASK, > diff --git > > a/drivers/gpu/drm/i915/display/intel_writeback_reg.h > > b/drivers/gpu/drm/i915/display/intel_writeback_reg.h > > index 5e7c6c99d191..f526af0f9aff 100644 > > --- a/drivers/gpu/drm/i915/display/intel_writeback_reg.h > > +++ b/drivers/gpu/drm/i915/display/intel_writeback_reg.h > > @@ -60,6 +60,7 @@ > > _WD_STRIDE_0,\ > > _WD_STRIDE_1) > > #define WD_STRIDE_MASK REG_GENMASK(15, 6) > > +#define WD_STRIDE_VAL(val) > REG_FIELD_PREP(WD_STRIDE_MASK, val) > > > > #define _WD_STREAMCAP_CTL0 0x6e590 > > #define _WD_STREAMCAP_CTL1 0x6ed90 > > -- > > 2.34.1 > > -- > Ville Syrjälä > Intel
