On Wed, Mar 11, 2026 at 05:06:03PM +0530, Ankit Nautiyal wrote:
> DP v2.1 mentions support for FAVT payload fields parsing in DPCD 0x2214
> Bit 2. This essentially signals the support for AS SDP version 2, that
> allows source to set the version in HB2[4:0] and the payload length in
> HB3[5:0] of the AS SDP header.
>
> Read this bit and store the AS SDP v2 capability in intel_dp.
>
> Signed-off-by: Ankit Nautiyal <[email protected]>
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++++
> 2 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e189f8c39ccb..d783cea06aed 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1870,6 +1870,7 @@ struct intel_dp {
> /* connector directly attached - won't be use for modeset in mst world
> */
> struct intel_connector *attached_connector;
> bool as_sdp_supported;
> + bool as_sdp_v2_supported;
>
> struct drm_dp_tunnel *tunnel;
> bool tunnel_suspended:1;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0d2403d48528..e6148e7f0ebc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6291,6 +6291,24 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
> false);
> }
>
> +static bool
> +intel_dp_sink_supports_as_sdp_v2(struct intel_dp *intel_dp)
> +{
> + struct intel_display *display = to_intel_display(intel_dp);
> + u8 rx_features;
> +
> + if (drm_dp_dpcd_read_byte(&intel_dp->aux,
> + DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
> + &rx_features) < 0) {
> + drm_dbg_kms(display->drm,
> + "Failed to read
> DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n");
> +
> + return false;
> + }
> +
> + return rx_features & DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED;
Hmm. So the name seems to imply it's only about the FAVT stuff.
But even when running in AVT mode some of the payload bytes
can still be valid. Dunno how much the other stuff actually matters
for VRR itself, but I think for PR the coasting vtotal would at
least be important if we don't send AS SDP while in PR active
state.
The problematic case would be if we have to send the AS SDP
for VRR purposes, but want to suspend it during PR active
for power savings, assuming the sink has the
!ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR capability.
So I suppose we might want to also check for PR+ALPM here,
in case some of those don't also set the
DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED bit.
Sadly there doesn't seem to be a proper AS SDP v2 supported
bit anywhere. We just have to guess based on other capabilities :(
> +}
> +
> static void
> intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
> {
> @@ -6298,6 +6316,9 @@ intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
>
> intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
> drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
> +
> + intel_dp->as_sdp_v2_supported = intel_dp->as_sdp_supported &&
> +
> intel_dp_sink_supports_as_sdp_v2(intel_dp);
> }
>
> static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool
> force_on_external)
> --
> 2.45.2
--
Ville Syrjälä
Intel
