> -----Original Message----- > From: Kandpal, Suraj <[email protected]> > Sent: Thursday, 12 March 2026 5.30 > To: Kahola, Mika <[email protected]>; [email protected]; > [email protected] > Cc: B S, Karthik <[email protected]>; Sharma, Swati2 > <[email protected]> > Subject: RE: [PATCH v3 00/24] Refactor LT PHY PLL handling to use DPLL > framework > > > Subject: [PATCH v3 00/24] Refactor LT PHY PLL handling to use DPLL > > framework > > > > This is v3 of [1], with the following changes > > - Reorder patches to maintain bisectability > > - Drop xe3plpd specific DDI enable_clock/disable_clock hooks and reuse > > MTL intel_mtl_pll_enable_clock() and intel_mtl_pll_disable_clock() > > hooks instead > > - Commit message updates > > Series Rb'd. > I would also like a Tested-by from the validation team after local validation > to make sure No regressions come in later. Before > we go ahead with merge
Thanks Suraj for these reviews. I will fix these checkpatch warnings and spin another round for CI before merging these patches. -Mika- > > Regards, > Suraj Kandpal > > > > > Mika Kahola (24): > > drm/i915/lt_phy: Dump missing PLL state parameters > > drm/i915/lt_phy: Add check if PLL is enabled > > drm/i915/lt_phy: Add PLL information for xe3plpd > > drm/i915/lt_phy: Refactor LT PHY PLL handling to use explicit PLL > > state > > drm/i915/lt_phy: Add lane_count to PLL state > > drm/i915/lt_phy: Add xe3plpd .compute_dplls hook > > drm/i915/lt_phy: Add xe3plpd .get_dplls hook > > drm/i915/lt_phy: Add xe3plpd .put_dplls hook > > drm/i915/lt_phy: Add xe3plpd .update_active_dpll hook > > drm/i915/lt_phy: Add xe3plpd .update_dpll_ref_clks hook > > drm/i915/lt_phy: Add xe3plpd .dump_hw_state hook > > drm/i915/lt_phy: Add xe3plpd .compare_hw_state hook > > drm/i915/lt_phy: Add xe3plpd .get_hw_state hook > > drm/i915/lt_phy: Add xe3plpd .get_freq hook > > drm/i915/lt_phy: Add xe3plpd .crtc_get_dpll > > drm/i915/lt_phy: Add .enable_clock hook on DDI > > drm/i915/lt_phy: Add .disable_clock hook on DDI > > drm/i915/lt_phy: Dump lane count for HW state > > drm/i915/lt_phy: Readout lane count > > drm/i915/lt_phy: Get encoder configuration for xe3plpd platform > > drm/i915/lt_phy: Add xe3plpd Thunderbolt PLL hooks > > drm/i915/lt_phy: Remove LT PHY specific state verification > > drm/i915/lt_phy: Enable dpll framework for xe3plpd > > drm/i915/lt_phy: Replace crtc compute clock > > > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +- > > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 + > > drivers/gpu/drm/i915/display/intel_ddi.c | 26 +-- > > drivers/gpu/drm/i915/display/intel_display.c | 32 --- > > drivers/gpu/drm/i915/display/intel_dpll.c | 26 +-- > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 184 ++++++++++++++++- > > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + > > drivers/gpu/drm/i915/display/intel_lt_phy.c | 193 ++++++++++-------- > > drivers/gpu/drm/i915/display/intel_lt_phy.h | 23 ++- > > .../drm/i915/display/intel_modeset_verify.c | 1 - > > 10 files changed, 318 insertions(+), 179 deletions(-) > > > > -- > > 2.43.0
