On Wed, 2026-02-25 at 09:51 +0530, Nautiyal, Ankit K wrote: > > On 2/19/2026 6:37 PM, Jouni Högander wrote: > > Add DSC_SU_PARAMETER_SET_0_DSC0 and DSC_SU_PARAMETER_SET_0_DSC1 > > register > > definitions for Selective Update Early Transport configuration. > > > > Bspec: 71709 > > Signed-off-by: Jouni Högander <[email protected]> > > --- > > drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 ++++++++++++ > > 1 file changed, 12 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > index 8afbf5a38335..3d1523dece8b 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > @@ -266,6 +266,18 @@ > > #define _PIPE_SRCSZ_ERLY_TPT_B 0x71074 > > #define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), > > _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B) > > > > +#define _DSC_SU_PARAMETER_SET_0_DSC0_A 0x78064 > > > I understand these are needed for PSR SU region, but these seem to > belong to DSC registers file with other DSC registers.
I also considered to place it there and decided this would be more clear as Early Transport specific and written only in intel_psr.c. PIPE_SRCSZ_ERLY_TPT is here as well. You can't even find definition in Bsec DSC documentation (see Bspec 68912) We can consider moving these later (PIPE_SRCSZ_ERLY_TPT and DSC_SU_PARAMETER_SE_0) at once and move configuration of them from intel_psr.c. Thought I'm not sure if we want todo that. What do you think? BR, Jouni Högander > > > Regards, > > Ankit > > > +#define _DSC_SU_PARAMETER_SET_0_DSC0_B 0x78264 > > +#define DSC_SU_PARAMETER_SET_0_DSC0(pipe) _MMIO_PIPE((pipe), > > _DSC_SU_PARAMETER_SET_0_DSC0_A, _DSC_SU_PARAMETER_SET_0_DSC0_B) > > +#define > > DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME_MASK REG_GENMASK(31, 20) > > +#define > > DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME(rows) > > REG_FIELD_PREP(DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME_MASK,(rows)) > > +#define > > DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT_MASK REG_GENMASK(15, 0) > > +#define > > DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT(h) > > REG_FIELD_PREP(DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT_MASK,(h)) > > + > > +#define _DSC_SU_PARAMETER_SET_0_DSC1_A 0x78164 > > +#define _DSC_SU_PARAMETER_SET_0_DSC1_B 0x78364 > > +#define DSC_SU_PARAMETER_SET_0_DSC1(pipe) _MMIO_PIPE((pipe), > > _DSC_SU_PARAMETER_SET_0_DSC1_A, _DSC_SU_PARAMETER_SET_0_DSC1_B) > > + > > #define _PR_ALPM_CTL_A 0x60948 > > #define PR_ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, > > tran, _PR_ALPM_CTL_A) > > #define > > PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU BIT(6)
