On Fri, Apr 11, 2014 at 11:09:03AM +0200, Daniel Vetter wrote:
> So not yet sold on the story here, at least for gen8/bdw. Apparently
> people haven't screamed about this yet, so it probably works.
Having thought about it a bit more, I don't see how the CPU side would
know about the tiling layout of the surfaces it accesses, so the
remaining options I see:
- we still need to swizzle the address on the CPU side
- bit 6 swizzling for X/Y tiling is just gone and the optimal use of
the RAM is left to the memory controller. If that's the case, we
should see things failing soon enough
So, until any failure case, meh. Just one thing to remember is that the
swizzling bits we set are possibly reserved and may be no-ops.
--
Damien
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