> -----Original Message-----
> From: Sousa, Gustavo <gustavo.so...@intel.com>
> Sent: Saturday, September 20, 2025 2:31 AM
> To: Bhadane, Dnyaneshwar <dnyaneshwar.bhad...@intel.com>; intel-
> g...@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Bhadane, Dnyaneshwar <dnyaneshwar.bhad...@intel.com>
> Subject: Re: [PATCH v2 3/3] drm/i915/xe3: Restrict PTL
> intel_encoder_is_c10phy() to only PHY A
> 
> Quoting Dnyaneshwar Bhadane (2025-09-19 13:22:33-03:00)
> >On PTL, no combo PHY is connected to PORT B. However, PORT B can still
> >be used for Type-C and will utilize the C20 PHY for eDP over Type-C. In
> >such configurations, VBTs also enumerate PORT B.
> >
> >This leads to issues where PORT B is incorrectly identified as using
> >the
> >C10 PHY, due to the assumption that returning true for PORT B in
> >intel_encoder_is_c10phy() would not cause problems.
> >
> >From PTL's perspective, only PORT A/PHY A uses the C10 PHY.
> >
> >Update the helper intel_encoder_is_c10phy() to return true only for
> >PORT A/PHY on PTL.
> >
> >Bspec: 72571,73944
> >Fixes: 9d10de78a37f ("drm/i915/wcl: C10 phy connected to port A and B")
> >Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhad...@intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ++++-------
> > 1 file changed, 4 insertions(+), 7 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >index 801235a5bc0a..e8b354d1c513 100644
> >--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >@@ -39,13 +39,10 @@ bool intel_encoder_is_c10phy(struct intel_encoder
> *encoder)
> >         struct intel_display *display = to_intel_display(encoder);
> >         enum phy phy = intel_encoder_to_phy(encoder);
> >
> >-        /* PTL doesn't have a PHY connected to PORT B; as such,
> >-         * there will never be a case where PTL uses PHY B.
> >-         * WCL uses PORT A and B with the C10 PHY.
> >-         * Reusing the condition for WCL and extending it for PORT B
> >-         * should not cause any issues for PTL.
> >-         */
> >-        if (display->platform.pantherlake && phy < PHY_C)
> >+        if (display->platform.pantherlake && phy == PHY_A)
> >+                return true;
> 
> While we know that WCL will return true for PHY_A here, this might not be so
> obvious...
> 
> >+
> >+        if (display->platform.pantherlake_wildcatlake && phy == PHY_B)
> >                 return true;
> 
> 
> ...so, what about something like below?
> 
>     if (display->platform.pantherlake) {
>         if (display->platform.pantherlake_wildcatlake)
>             return phy <= PHY_B;
>         else
>             return phy == PHY_A;
>     }
Yes thanks , Updated the condition of wcl/ptl as mentioned.
> 
> We could also update the style for MTL and LNL in a follow-up patch...
Yeh we will update in the separate patch apart from this series. 

Dnyaneshwar
> 
> --
> Gustavo Sousa
> 
> >
> >         if ((display->platform.lunarlake ||
> >display->platform.meteorlake) && phy < PHY_C)
> >--
> >2.51.0
> >

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