-----Original Message-----
From: Shankar, Uma <uma.shan...@intel.com>
Sent: Wednesday, September 3, 2025 1:23 AM
To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
Cc: ville.syrj...@linux.intel.com; Govindapillai, Vinod
<vinod.govindapil...@intel.com>; Cavitt, Jonathan <jonathan.cav...@intel.com>;
Shankar, Uma <uma.shan...@intel.com>; Srinivas, Vidya <vidya.srini...@intel.com>
Subject: [v3 1/1] drm/i915/display: Remove FBC modulo 4 restriction for ADL-P+
>
> FBC restriction where FBC is disabled for non-modulo 4 plane size
> (including plane size + yoffset) is fixed from ADL-P onwards in h/w.
NIT:
Since the above sentence is just a repeat of something said in the below
paragraph, we could debatably remove it from the commit message entirely.
It's not worth blocking over, though, so:
Reviewed-by: Jonathan Cavitt <jonathan.cav...@intel.com>
-Jonathan Cavitt
>
> WA:22010751166 does not apply past display version 12. Or, in
> other words, the FBC restriction where FBC is disabled for
> non-modulo 4 plane sizes (including plane size + yoffset) is fixed
> from display version 13 and onwards. Relax the restriction for the same.
>
> v3: Update comments for clarity (Jonathan Cavitt)
>
> v2: Update the macro for display version check (Vinod)
>
> Suggested-by: Vidya Srinivas <vidya.srini...@intel.com>
> Signed-off-by: Uma Shankar <uma.shan...@intel.com>
> Reviewed-by: Vinod Govindapillai <vinod.govindapil...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index d4c5deff9cbe..9e097ed80bd1 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1550,14 +1550,14 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> * having a Y offset that isn't divisible by 4 causes FIFO underrun
> * and screen flicker.
> */
> - if (DISPLAY_VER(display) >= 9 &&
> + if (IS_DISPLAY_VER(display, 9, 12) &&
> plane_state->view.color_plane[0].y & 3) {
> plane_state->no_fbc_reason = "plane start Y offset misaligned";
> return 0;
> }
>
> /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
> - if (DISPLAY_VER(display) >= 11 &&
> + if (IS_DISPLAY_VER(display, 9, 12) &&
> (plane_state->view.color_plane[0].y +
> (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {
> plane_state->no_fbc_reason = "plane end Y offset misaligned";
> --
> 2.42.0
>
>
