> -----Original Message-----
> From: Intel-xe <intel-xe-boun...@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Tuesday, 5 August 2025 12.18
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nik...@intel.com>
> Subject: [PATCH 02/12] drm/i915: add vlv_clock_get_czclk()
>
> Add vlv_clock_get_czclk() helper to avoid looking at i915->czclk_freq
> directly.
>
Reviewed-by: Mika Kahola <mika.kah...@intel.com>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 3 +--
> drivers/gpu/drm/i915/display/intel_display.c | 20 ++++++++++++++------
> drivers/gpu/drm/i915/display/intel_display.h | 1 +
> drivers/gpu/drm/i915/gt/intel_rc6.c | 3 ++-
> drivers/gpu/drm/i915/gt/intel_rps.c | 3 ++-
> 5 files changed, 20 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 59997dc95984..8f6b31bfe7c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -629,7 +629,6 @@ static void vlv_get_cdclk(struct intel_display *display,
>
> static void vlv_program_pfi_credits(struct intel_display *display) {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> unsigned int credits, default_credits;
>
> if (display->platform.cherryview)
> @@ -637,7 +636,7 @@ static void vlv_program_pfi_credits(struct intel_display
> *display)
> else
> default_credits = PFI_CREDIT(8);
>
> - if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
> + if (display->cdclk.hw.cdclk >= vlv_clock_get_czclk(display->drm)) {
> /* CHV suggested value is 31 or 63 */
> if (display->platform.cherryview)
> credits = PFI_CREDIT_63;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index fdd29d9256ed..117b6c423a4c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -186,25 +186,33 @@ int vlv_get_cck_clock_hpll(struct drm_device *drm,
> return hpll;
> }
>
> -int vlv_clock_get_gpll(struct drm_device *drm)
> +int vlv_clock_get_czclk(struct drm_device *drm)
> {
> struct drm_i915_private *i915 = to_i915(drm);
>
> + if (!i915->czclk_freq)
> + i915->czclk_freq = vlv_get_cck_clock_hpll(drm, "czclk",
> + CCK_CZ_CLOCK_CONTROL);
> +
> + return i915->czclk_freq;
> +}
> +
> +int vlv_clock_get_gpll(struct drm_device *drm) {
> return vlv_get_cck_clock(drm, "GPLL ref", CCK_GPLL_CLOCK_CONTROL,
> - i915->czclk_freq);
> + vlv_clock_get_czclk(drm));
> }
>
> void intel_update_czclk(struct intel_display *display) {
> - struct drm_i915_private *dev_priv = to_i915(display->drm);
> + int czclk_freq;
>
> if (!display->platform.valleyview && !display->platform.cherryview)
> return;
>
> - dev_priv->czclk_freq = vlv_get_cck_clock_hpll(display->drm, "czclk",
> - CCK_CZ_CLOCK_CONTROL);
> + czclk_freq = vlv_clock_get_czclk(display->drm);
>
> - drm_dbg_kms(display->drm, "CZ clock rate: %d kHz\n",
> dev_priv->czclk_freq);
> + drm_dbg_kms(display->drm, "CZ clock rate: %d kHz\n", czclk_freq);
> }
>
> static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) diff
> --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 7ae899b8787a..811066a9e69d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -440,6 +440,7 @@ int vlv_get_cck_clock(struct drm_device *drm,
> const char *name, u32 reg, int ref_freq); int
> vlv_get_cck_clock_hpll(struct drm_device *drm,
> const char *name, u32 reg);
> +int vlv_clock_get_czclk(struct drm_device *drm);
> int vlv_clock_get_gpll(struct drm_device *drm); bool
> intel_has_pending_fb_unpin(struct intel_display *display); void
> intel_encoder_destroy(struct drm_encoder *encoder); diff --git
> a/drivers/gpu/drm/i915/gt/intel_rc6.c
> b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 9ca42589da4d..0fd23b04d3f9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -6,6 +6,7 @@
> #include <linux/pm_runtime.h>
> #include <linux/string_helpers.h>
>
> +#include "display/intel_display.h"
> #include "gem/i915_gem_region.h"
> #include "i915_drv.h"
> #include "i915_reg.h"
> @@ -802,7 +803,7 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum
> intel_rc6_res_type id)
> /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> mul = 1000000;
> - div = i915->czclk_freq;
> + div = vlv_clock_get_czclk(&i915->drm);
> overflow_hw = BIT_ULL(40);
> time_hw = vlv_residency_raw(uncore, reg);
> } else {
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index e2b5cdf6b7cb..664ffe02dc28 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -1770,6 +1770,7 @@ static void vlv_c0_read(struct intel_uncore *uncore,
> struct intel_rps_ei *ei)
>
> static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32 pm_iir) {
> + struct drm_i915_private *i915 = rps_to_i915(rps);
> struct intel_uncore *uncore = rps_to_uncore(rps);
> const struct intel_rps_ei *prev = &rps->ei;
> struct intel_rps_ei now;
> @@ -1786,7 +1787,7 @@ static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32
> pm_iir)
>
> time = ktime_us_delta(now.ktime, prev->ktime);
>
> - time *= rps_to_i915(rps)->czclk_freq;
> + time *= vlv_clock_get_czclk(&i915->drm);
>
> /* Workload can be split between render + media,
> * e.g. SwapBuffers being blitted in X after being rendered in
> --
> 2.39.5
