When DSC is enabled on a pipe, the pipe pixel rate input to the
CDCLK frequency and pipe joining calculation needs an adjustment to
account for compression overhead "bubbles" added at each horizontal
slice boundary.
Bspec:68912
Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 45 +++++++++++++++++++++--
1 file changed, 41 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 8e799e225af1..7513cecdeaf3 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1034,15 +1034,52 @@ void intel_vdsc_state_dump(struct drm_printer *p, int
indent,
drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
}
+static
+int intel_dsc_get_pixel_rate_with_dsc_bubbles(int pixel_rate, int htotal,
+ int dsc_horizontal_slices)
+{
+ int dsc_slice_factor_x100;
+ int dsc_slice_bubbles;
+
+ if (!htotal)
+ return 0;
+
+ dsc_slice_bubbles = 14 * dsc_horizontal_slices;
+ dsc_slice_factor_x100 = (100 * htotal + dsc_slice_bubbles) / htotal;
+
+ return (dsc_slice_factor_x100 * pixel_rate) / 100;
+}
+
+static
+int pixel_rate_with_dsc_bubbles(const struct intel_crtc_state *crtc_state, int
pixel_rate)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
+ const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+ int dsc_horizontal_slices;
+
+ if (drm_WARN_ON(display->drm, !vdsc_cfg->slice_width))
+ return 0;
+
+ dsc_horizontal_slices = vdsc_cfg->pic_width / vdsc_cfg->slice_width;
+
+ return intel_dsc_get_pixel_rate_with_dsc_bubbles(pixel_rate,
+ adjusted_mode->htotal,
+ dsc_horizontal_slices);
+}
+
int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
+ int pixel_rate;
int min_cdclk;
if (!crtc_state->dsc.compression_enable)
return 0;
+ pixel_rate = pixel_rate_with_dsc_bubbles(crtc_state,
crtc_state->pixel_rate);
+
/*
* When we decide to use only one VDSC engine, since
* each VDSC operates with 1 ppc throughput, pixel clock
@@ -1050,7 +1087,7 @@ int intel_vdsc_min_cdclk(const struct intel_crtc_state
*crtc_state)
* If there 2 VDSC engines, then pixel clock can't be higher than
* VDSC clock(cdclk) * 2 and so on.
*/
- min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances);
+ min_cdclk = DIV_ROUND_UP(pixel_rate, num_vdsc_instances);
if (crtc_state->joiner_pipes) {
int pixel_clock =
intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
@@ -1068,9 +1105,9 @@ int intel_vdsc_min_cdclk(const struct intel_crtc_state
*crtc_state)
* => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner
Interface bits
*/
int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36
: 24;
- int min_cdclk_bj =
-
(fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
- pixel_clock) / (2 * bigjoiner_interface_bits);
+ int adjusted_pixel_rate =
pixel_rate_with_dsc_bubbles(crtc_state, pixel_clock);
+ int min_cdclk_bj =
(fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
+ adjusted_pixel_rate) / (2 *
bigjoiner_interface_bits);
min_cdclk = max(min_cdclk, min_cdclk_bj);
}
--
2.45.2
