On g4x, we have an issue where the register write to setup the rings do not always take. However, it appears that the current check also passes only by chance, a second reading of the register returns a different broekn value - but the GPU appears to function. Based on that observation, lets try feeding a nop into the ring and seeing if it advances as part of our startup sanity checks.
References: https://bugs.freedesktop.org/show_bug.cgi?id=76554 Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index a8c73a0d935d..bc52645fa8d5 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -514,10 +514,14 @@ static int init_ring_common(struct intel_ring_buffer *ring) ((ring->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID); + iowrite32(MI_NOOP, ring->virtual_start + 0); + iowrite32(MI_NOOP, ring->virtual_start + 4); + ring->write_tail(ring, 8); + /* If the head is still not zero, the ring is dead */ if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && - (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { + (I915_READ_HEAD(ring) & HEAD_ADDR) == 8, 50)) { DRM_ERROR("%s initialization failed " "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", ring->name, -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
