Get the ggtt_offset of the drm_framebuffer which needs to be
written to the surface base address bits of WD_SURF register.
Signed-off-by: Suraj Kandpal <suraj.kand...@intel.com>
---
drivers/gpu/drm/i915/display/intel_writeback.c | 3 +++
drivers/gpu/drm/i915/display/intel_writeback_reg.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_writeback.c
b/drivers/gpu/drm/i915/display/intel_writeback.c
index c6c05bd3d298..0f26134beacd 100644
--- a/drivers/gpu/drm/i915/display/intel_writeback.c
+++ b/drivers/gpu/drm/i915/display/intel_writeback.c
@@ -286,6 +286,9 @@ static void intel_writeback_capture(struct
intel_atomic_state *state,
val = DIV_ROUND_UP((adjusted_mode->hdisplay * bpp), 64);
intel_de_write(display, WD_STRIDE(trans), WD_STRIDE_VAL(val));
+ val = i915_ggtt_offset(wb_job->vma);
+ intel_de_write(display, WD_SURF(trans), val);
+
val = 0;
val |= START_TRIGGER_FRAME | WD_FRAME_NUMBER(wb_conn->frame_num);
intel_de_rmw(display, WD_TRANS_FUNC_CTL(trans),
diff --git a/drivers/gpu/drm/i915/display/intel_writeback_reg.h
b/drivers/gpu/drm/i915/display/intel_writeback_reg.h
index f526af0f9aff..403f9b64015b 100644
--- a/drivers/gpu/drm/i915/display/intel_writeback_reg.h
+++ b/drivers/gpu/drm/i915/display/intel_writeback_reg.h
@@ -81,6 +81,8 @@
#define WD_SURF(tc) _MMIO_WD(tc,\
_WD_SURF_0,\
_WD_SURF_1)
+#define WD_SURF_ADDR_MASK REG_GENMASK(31, 12)
+#define WD_SURF_ADDR(val) REG_FIELD_PREP(WD_SURF_ADDR_MASK, val)
#define _WD_IMR_0 0x6e560
#define _WD_IMR_1 0x6ed60
--
2.34.1
