Use recommended static values as per wa_14021694213 for min_hblank to avoid underruns.
v2: corrected checkpatch warning and retain the restriction for min_hblank (Jani) Bspec: 74379 Signed-off-by: Arun R Murthy <arun.r.mur...@intel.com> --- Changes in v2: - EDITME: describe what is new in this series revision. - EDITME: use bulletpoints and terse descriptions. - Link to v1: https://lore.kernel.org/r/20250624-min_hblank-v1-1-5c100e4a8...@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 62 ++++++--------------------------- 1 file changed, 10 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f48912f308df7fd26c9d089e8f1bd096bfc8df95..b657340648cd2be72cec3fae606c0bc2ec8dba3d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3115,22 +3115,7 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(crtc_state); - const struct drm_display_mode *adjusted_mode = - &crtc_state->hw.adjusted_mode; - struct intel_connector *connector = to_intel_connector(conn_state->connector); - int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8; - /* - * min symbol cycles is 3(BS,VBID, BE) for 128b/132b and - * 5(BS, VBID, MVID, MAUD, BE) for 8b/10b - */ - int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5; bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); - int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state); - int min_hblank; - int max_lane_count = 4; - int hactive_sym_cycles, htotal_sym_cycles; - int dsc_slices = 0; - int link_bpp_x16; if (DISPLAY_VER(display) < 30) return 0; @@ -3139,45 +3124,18 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state, if (!is_mst && !intel_dp_is_uhbr(crtc_state)) return 0; - if (crtc_state->dsc.compression_enable) { - dsc_slices = intel_dp_dsc_get_slice_count(connector, - adjusted_mode->crtc_clock, - adjusted_mode->crtc_hdisplay, - num_joined_pipes); - if (!dsc_slices) { - drm_dbg(display->drm, "failed to calculate dsc slice count\n"); - return -EINVAL; - } + /* min_hblank formula is undergoing a change and the recomendation is to use static value */ + if (intel_dp_is_uhbr(crtc_state)) { + if (crtc_state->dsc.compression_enable && + crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && + crtc_state->pipe_bpp == 18) + crtc_state->min_hblank = 2; + else + crtc_state->min_hblank = 3; + } else { + crtc_state->min_hblank = 10; } - if (crtc_state->dsc.compression_enable) - link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16; - else - link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format, - crtc_state->pipe_bpp)); - - /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */ - hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count, - adjusted_mode->hdisplay, - dsc_slices, - link_bpp_x16, - symbol_size, is_mst); - htotal_sym_cycles = adjusted_mode->htotal * hactive_sym_cycles / - adjusted_mode->hdisplay; - - min_hblank = htotal_sym_cycles - hactive_sym_cycles; - /* minimum Hblank calculation: https://groups.vesa.org/wg/DP/document/20494 */ - min_hblank = max(min_hblank, min_sym_cycles); - - /* - * adjust the BlankingStart/BlankingEnd framing control from - * the calculated value - */ - min_hblank = min_hblank - 2; - - min_hblank = min(10, min_hblank); - crtc_state->min_hblank = min_hblank; - return 0; } --- base-commit: da56936fad6f5e1d5f0cef8b50277bfb071eefe7 change-id: 20250624-min_hblank-8af8d2626ff8 Best regards, -- Arun R Murthy <arun.r.mur...@intel.com>
