> -----Original Message-----
> From: Intel-xe <intel-xe-boun...@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Monday, June 9, 2025 7:41 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: intel...@lists.freedesktop.org
> Subject: [PATCH v4 09/21] drm/i915: Set PKG_C_LATENCY.added_wake_time to
> 0
>
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> AFAIK PKG_C_LATENCY.added_wake_time only matters for flip queue.
> As long as we're not using that there's no point in adding any extra wake
> time.
Agree.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shan...@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 9 ---------
> 1 file changed, 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 2c2371574d6f..bf1372024efd 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -32,12 +32,6 @@
> #include "skl_watermark.h"
> #include "skl_watermark_regs.h"
>
> -/*It is expected that DSB can do posted writes to every register in
> - * the pipe and planes within 100us. For flip queue use case, the
> - * recommended DSB execution time is 100us + one SAGV block time.
> - */
> -#define DSB_EXE_TIME 100
> -
> static void skl_sagv_disable(struct intel_display *display);
>
> /* Stores plane specific WM parameters */ @@ -2949,9 +2943,6 @@
> intel_program_dpkgc_latency(struct intel_atomic_state *state)
> }
>
> if (fixed_refresh_rate) {
> - added_wake_time = DSB_EXE_TIME +
> - display->sagv.block_time_us;
> -
> latency = skl_watermark_max_latency(display, 1);
>
> /* Wa_22020432604 */
> --
> 2.49.0
