> -----Original Message----- > From: Intel-xe <intel-xe-boun...@lists.freedesktop.org> On Behalf Of Ville > Syrjala > Sent: Monday, June 9, 2025 7:41 PM > To: intel-gfx@lists.freedesktop.org > Cc: intel...@lists.freedesktop.org > Subject: [PATCH v4 08/21] drm/i915/dmc: Parametrize > MTL_PIPEDMC_GATING_DIS > > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > The MTL+ PIPEDMC clock gating bits can be parametrized. > Make it so.
Looks Good to me. Reviewed-by: Uma Shankar <uma.shan...@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dmc.c | 3 ++- > drivers/gpu/drm/i915/i915_reg.h | 3 +-- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c > b/drivers/gpu/drm/i915/display/intel_dmc.c > index b6ac480f391c..6392fa928e08 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc.c > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c > @@ -482,7 +482,8 @@ static void mtl_pipedmc_clock_gating_wa(struct > intel_display *display) > * for pipe A and B. > */ > intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, > - MTL_PIPEDMC_GATING_DIS_A | > MTL_PIPEDMC_GATING_DIS_B); > + MTL_PIPEDMC_GATING_DIS(PIPE_A) | > + MTL_PIPEDMC_GATING_DIS(PIPE_B)); > } > > static void pipedmc_clock_gating_wa(struct intel_display *display, bool > enable) > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h index > 52a902532e6f..04fb40867cc0 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -763,8 +763,7 @@ > */ > #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) > #define DARBF_GATING_DIS REG_BIT(27) > -#define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15) > -#define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14) > +#define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe)) > #define PWM2_GATING_DIS REG_BIT(14) > #define PWM1_GATING_DIS REG_BIT(13) > > -- > 2.49.0
