From: Suraj Kandpal <suraj.kand...@intel.com>
We only support resolution upto 4k for single pipe when using
YUV420 format so we prune these modes and restrict the plane size
at src.
Signed-off-by: Suraj Kandpal <suraj.kand...@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atw...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 205ec315b413..8bccc6e0b5b3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1396,6 +1396,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
struct intel_display *display = to_intel_display(_connector->dev);
struct intel_connector *connector = to_intel_connector(_connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
+ enum intel_output_format sink_format;
const struct drm_display_mode *fixed_mode;
int target_clock = mode->clock;
int max_rate, mode_rate, max_lanes, max_link_clock;
@@ -1429,6 +1430,13 @@ intel_dp_mode_valid(struct drm_connector *_connector,
mode->hdisplay,
target_clock);
max_dotclk *= num_joined_pipes;
+ sink_format = intel_dp_sink_format(connector, mode);
+ if (num_joined_pipes == 1) {
+ if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
+ mode->hdisplay > 4096)
+ return MODE_NO_420;
+ }
+
if (target_clock > max_dotclk)
return MODE_CLOCK_HIGH;
@@ -1444,10 +1452,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
intel_dp_mode_min_output_bpp(connector, mode));
if (intel_dp_has_dsc(connector)) {
- enum intel_output_format sink_format, output_format;
+ enum intel_output_format output_format;
int pipe_bpp;
- sink_format = intel_dp_sink_format(connector, mode);
output_format = intel_dp_output_format(connector, sink_format);
/*
* TBD pass the connector BPC,
--
2.45.0
