>From PTL, LUT registers are made double buffered. This helps us
to program them in the active region without any concern of tearing.
This particulary helps in case of displays with high refresh rates
where vblank periods are shorter.
This series
- adds MMIO programming of LUT registers in active region
- removes wait for vblank in invocation of DSB1 to
program LUT registers in DSB programming path.
This is a follow-up to the RFC series [1]
[1] https://patchwork.freedesktop.org/series/142437/
Chaitanya Kumar Borah (2):
drm/i915/display: Add MMIO path for double-buffered LUT registers
drm/i915/display: Don't wait for vblank for LUT DSB programming
drivers/gpu/drm/i915/display/intel_color.c | 4 ++++
drivers/gpu/drm/i915/display/intel_crtc.c | 4 +++-
drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++--
drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
4 files changed, 16 insertions(+), 3 deletions(-)
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2.25.1
