On Thu, 2025-02-13 at 08:47 +0200, Jouni Högander wrote: > This patch set is doing necessary modifications to support PSR update > using DSB on LunarLake onwards > > It is not necessary to wait for PSR1 to idle or PSR2 to exit DEEP > sleep at the begin of commit This is left out from DSB commit. There > might be room for optimization for non-DSB as well because such wait > is not supposed to be necessary at the begin of update. > > PSR mutex is not locked when performing DSB commit. It is not > necessary as we are currently using DSB only when sending updates > towards panel. I.e. not using it when changing PSR mode. Also > necessary changes are made to use PSR2_MAN_TRK_CTL only in > DSB. Frontbuffer updates and legacy cursor updates are using SFF_CTL > register to perform full frame updates. > > DSB_SKIP_WAITS_EN is removed to ensure all waits are performed when > PSR is active. PSR "Frame Change" event is manually triggered at the > begin of each DSB commit by adding CURSURFLIVE register write. > > Possibe problem with DSB commit when PSR is already waking up is > avoided by evading scanline 0.
These are now pushed to drm-intel-next. Thank you Ville and Animesh for your reviews. BR, Jouni Högander > > v8: > - rebase > v7: > - Rename "drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when > DSB is in use" as "drm/i915/psr: Write PSR2_MAN_TRK_CTL on DSB > commit" due to scope changes. > - Warn on use_dsb in non-dsb pipe update functions > - dsb as a first parameter in intel_psr_trigger_frame_change_event > v6: > - add comment explaining why we are not setting DSB_SKIP_WAITS_EN > - add separate function to generate the "Frame change"evant. > - use intel_dsb_emit_wait_dsl > - add evasion of scanline 0 also for Panel Replay > v5: > - rebase > v4: > - remove DSB_SKIP_WAITS_EN > - Add CURSURFLIVE register write at the begin of DSB commit > - evade scanline 0 > v3: > - do not use DSB when PSR mode is changing > v2: > - use _MMIO_TRANS instead of _MMIO_TRANS2 > - drop evasion from intel_psr_configure_full_frame_update > > Jouni Högander (13): > drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update > drm/i915/psr: Rename psr_force_hw_tracking_exit as > intel_psr_force_update > drm/i915/psr: Split setting sff and cff bits away from > intel_psr_force_update > drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL > registers > drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards > drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB > drm/i915/psr: Write PSR2_MAN_TRK_CTL on DSB commit as well > drm/i915/display: Warn on use_dsb in non-dsb pipe update functions > drm/i915/psr: Remove DSB_SKIP_WAITS_EN chicken bit > drm/i915/display: Evade scanline 0 as well if PSR1 or PSR2 is > enabled > drm/i915/psr: Add function for triggering "Frame Change" event > drm/i915/display: Ensure we have "Frame Change" event in DSB commit > drm/i915/psr: Allow DSB usage when PSR is enabled > > drivers/gpu/drm/i915/display/intel_crtc.c | 4 + > drivers/gpu/drm/i915/display/intel_display.c | 21 ++- > drivers/gpu/drm/i915/display/intel_dsb.c | 27 +++- > drivers/gpu/drm/i915/display/intel_psr.c | 141 +++++++++------- > -- > drivers/gpu/drm/i915/display/intel_psr.h | 7 +- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++ > 6 files changed, 136 insertions(+), 74 deletions(-) >
