From: Ville Syrjälä <ville.syrj...@linux.intel.com>
The RING_FAULT bits have change a bit over the years. Document
which platforms use which bits.
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 764424d48a25..1d318993a652 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -326,10 +326,10 @@
_RING_FAULT_REG_VCS, \
_RING_FAULT_REG_VECS, \
_RING_FAULT_REG_BCS))
-#define RING_FAULT_ENGINE_ID_MASK REG_GENMASK(16, 12)
-#define RING_FAULT_GTTSEL_MASK REG_BIT(11)
+#define RING_FAULT_ENGINE_ID_MASK REG_GENMASK(16, 12) /* bdw+ */
+#define RING_FAULT_GTTSEL_MASK REG_BIT(11) /* pre-bdw */
#define RING_FAULT_SRCID_MASK REG_GENMASK(10, 3)
-#define RING_FAULT_FAULT_TYPE_MASK REG_GENMASK(2, 1)
+#define RING_FAULT_FAULT_TYPE_MASK REG_GENMASK(2, 1) /* ivb+ */
#define RING_FAULT_VALID REG_BIT(0)
#define ERROR_GEN6 _MMIO(0x40a0)
--
2.45.3
