[PATCH 7/8] drm/xe/vram: Use xe_force_wake guard helper

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst <d...@lankhorst.se>
---
 drivers/gpu/drm/xe/xe_vram.c | 45 ++++++++++++++++--------------------
 1 file changed, 20 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index b1f81dca610dc..9180bb4d29971 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -220,7 +220,6 @@ static int tile_vram_size(struct xe_tile *tile, u64 
*vram_size,
 {
        struct xe_device *xe = tile_to_xe(tile);
        struct xe_gt *gt = tile->primary_gt;
-       unsigned int fw_ref;
        u64 offset;
        u32 reg;
 
@@ -240,33 +239,29 @@ static int tile_vram_size(struct xe_tile *tile, u64 
*vram_size,
                return 0;
        }
 
-       fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
-       if (!fw_ref)
-               return -ETIMEDOUT;
-
-       /* actual size */
-       if (unlikely(xe->info.platform == XE_DG1)) {
-               *tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), 
LMEM_BAR);
-               *tile_offset = 0;
-       } else {
-               reg = xe_gt_mcr_unicast_read_any(gt, 
XEHP_TILE_ADDR_RANGE(gt->info.id));
-               *tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * SZ_1G;
-               *tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * SZ_1G;
-       }
-
-       /* minus device usage */
-       if (xe->info.has_flat_ccs) {
-               offset = get_flat_ccs_offset(gt, *tile_size);
-       } else {
-               offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE);
-       }
+       scoped_cond_guard(xe_force_wake_get, return -ETIMEDOUT, gt_to_fw(gt), 
XE_FW_GT) {
+               /* actual size */
+               if (unlikely(xe->info.platform == XE_DG1)) {
+                       *tile_size = pci_resource_len(to_pci_dev(xe->drm.dev), 
LMEM_BAR);
+                       *tile_offset = 0;
+               } else {
+                       reg = xe_gt_mcr_unicast_read_any(gt, 
XEHP_TILE_ADDR_RANGE(gt->info.id));
+                       *tile_size = (u64)REG_FIELD_GET(GENMASK(14, 8), reg) * 
SZ_1G;
+                       *tile_offset = (u64)REG_FIELD_GET(GENMASK(7, 1), reg) * 
SZ_1G;
+               }
 
-       /* remove the tile offset so we have just the available size */
-       *vram_size = offset - *tile_offset;
+               /* minus device usage */
+               if (xe->info.has_flat_ccs) {
+                       offset = get_flat_ccs_offset(gt, *tile_size);
+               } else {
+                       offset = xe_mmio_read64_2x32(&tile->mmio, GSMBASE);
+               }
 
-       xe_force_wake_put(gt_to_fw(gt), fw_ref);
+               /* remove the tile offset so we have just the available size */
+               *vram_size = offset - *tile_offset;
 
-       return 0;
+               return 0;
+       }
 }
 
 static void vram_fini(void *arg)
-- 
2.47.1