[PATCH 06/28] drm/i915/vrr: Fill VRR timing generator mode for CMRR and VRR

[Ankit Nautiyal]

Fill vrr.mode during compute_config and update intel_vrr_get_config() to
read vrr.mode based on CMRR and VRR enable conditions.

Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 1 +
 drivers/gpu/drm/i915/display/intel_vrr.c     | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index a6383ddde871..9cff080d4ff9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5803,6 +5803,7 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
 
        if (!fastset) {
                PIPE_CONF_CHECK_BOOL(vrr.enable);
+               PIPE_CONF_CHECK_X(vrr.mode);
                PIPE_CONF_CHECK_I(vrr.vmin);
                PIPE_CONF_CHECK_I(vrr.vmax);
                PIPE_CONF_CHECK_I(vrr.flipline);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 6f314e209e96..ded5466c5214 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -227,6 +227,7 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state 
*crtc_state)
 {
        crtc_state->vrr.enable = true;
        crtc_state->cmrr.enable = true;
+       crtc_state->vrr.mode = INTEL_VRRTG_MODE_CMRR;
        /*
         * TODO: Compute precise target refresh rate to determine
         * if video_mode_required should be true. Currently set to
@@ -243,6 +244,7 @@ static
 void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
 {
        crtc_state->vrr.enable = true;
+       crtc_state->vrr.mode = INTEL_VRRTG_MODE_VRR;
        crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
 
@@ -506,12 +508,15 @@ void intel_vrr_get_config(struct intel_crtc_state 
*crtc_state)
 
        if (HAS_CMRR(display) && trans_vrr_ctl & VRR_CTL_CMRR_ENABLE) {
                crtc_state->cmrr.enable = true;
+               crtc_state->vrr.mode = INTEL_VRRTG_MODE_CMRR;
                crtc_state->cmrr.cmrr_n =
                        intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, 
cpu_transcoder),
                                             TRANS_CMRR_N_HI(display, 
cpu_transcoder));
                crtc_state->cmrr.cmrr_m =
                        intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, 
cpu_transcoder),
                                             TRANS_CMRR_M_HI(display, 
cpu_transcoder));
+       } else if (trans_vrr_ctl & VRR_CTL_VRR_ENABLE) {
+               crtc_state->vrr.mode = INTEL_VRRTG_MODE_VRR;
        }
 
        if (DISPLAY_VER(display) >= 13)
-- 
2.45.2