Try SNPS_PHY HDMI alogorithm, if there are no pre-computed tables.
Also get rid of the helper to get rate for HDMI snps phy, as we no
longer depend only on pre-computed tables.
v2:
-Prefer pre-computed tables over computed values from algorithm. (Jani)
Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kand...@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 -
drivers/gpu/drm/i915/display/intel_snps_phy.c | 37 +++++--------------
drivers/gpu/drm/i915/display/intel_snps_phy.h | 1 -
3 files changed, 9 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 5ae678f4eaa7..9a4bc3c4611d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1918,8 +1918,6 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
*/
if (DISPLAY_VER(display) >= 14)
return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
- else if (IS_DG2(dev_priv))
- return intel_snps_phy_check_hdmi_link_rate(clock);
return MODE_OK;
}
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 41fe26dc200b..ec3c0ea2f4cb 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -11,6 +11,7 @@
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_snps_hdmi_pll.h"
#include "intel_snps_phy.h"
#include "intel_snps_phy_regs.h"
@@ -1788,24 +1789,9 @@ intel_mpllb_tables_get(struct intel_crtc_state
*crtc_state,
int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_mpllb_state * const *tables;
int i;
- if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
- if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock)
- != MODE_OK) {
- /*
- * FIXME: Can only support fixed HDMI frequencies
- * until we have a proper algorithm under a valid
- * license.
- */
- drm_dbg_kms(&i915->drm, "Can't support HDMI link rate
%d\n",
- crtc_state->port_clock);
- return -EINVAL;
- }
- }
-
tables = intel_mpllb_tables_get(crtc_state, encoder);
if (!tables)
return -EINVAL;
@@ -1817,6 +1803,14 @@ int intel_mpllb_calc_state(struct intel_crtc_state
*crtc_state,
}
}
+ /* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed
tables */
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+
intel_snps_hdmi_pll_compute_mpllb(&crtc_state->dpll_hw_state.mpllb,
+ crtc_state->port_clock);
+
+ return 0;
+ }
+
return -EINVAL;
}
@@ -1982,19 +1976,6 @@ void intel_mpllb_readout_hw_state(struct intel_encoder
*encoder,
pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN;
}
-int intel_snps_phy_check_hdmi_link_rate(int clock)
-{
- const struct intel_mpllb_state * const *tables = dg2_hdmi_tables;
- int i;
-
- for (i = 0; tables[i]; i++) {
- if (clock == tables[i]->clock)
- return MODE_OK;
- }
-
- return MODE_CLOCK_RANGE;
-}
-
void intel_mpllb_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h
b/drivers/gpu/drm/i915/display/intel_snps_phy.h
index bc08b92a7cd9..1dd564ed9fa8 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h
@@ -30,7 +30,6 @@ void intel_mpllb_readout_hw_state(struct intel_encoder
*encoder,
int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
const struct intel_mpllb_state *pll_state);
-int intel_snps_phy_check_hdmi_link_rate(int clock);
void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state);
void intel_mpllb_state_verify(struct intel_atomic_state *state,
--
2.45.2
