> -----Original Message-----
> From: Intel-xe <intel-xe-boun...@lists.freedesktop.org> On Behalf Of Ankit
> Nautiyal
> Sent: Thursday, October 10, 2024 9:41 AM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: jani.nik...@linux.intel.com; Shankar, Uma <uma.shan...@intel.com>
> Subject: [PATCH 1/4] Add bits for link_n_exended for DISPLAY >= 14
>
> LINK_N register has bits 31:24 for extended link N value used for
> HDMI2.1 and for an alternate mode of operation of DP TG DDA
> (Bspec:50488).
>
> Add support for these extra bits.
>
> v2: Drop extra link_n_ext member. (Jani)
> v3: Avoid link_n_ext in set_m_n helper. (Jani)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 17 +++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e1f6255e918b..2a7fa0013b44 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2721,14 +2721,21 @@ void intel_set_m_n(struct drm_i915_private
> *i915,
> i915_reg_t data_m_reg, i915_reg_t data_n_reg,
> i915_reg_t link_m_reg, i915_reg_t link_n_reg) {
> + u32 link_n = m_n->link_n;
> +
> intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n-
> >data_m);
> intel_de_write(i915, data_n_reg, m_n->data_n);
> intel_de_write(i915, link_m_reg, m_n->link_m);
> +
> + if (DISPLAY_VER(i915) >= 14)
> + link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
> + else
> + link_n &= DATA_LINK_M_N_MASK;
I think, (~PIPE_LINK_N1_EXTENDED_MASK) and DATA_LINK_M_N_MASK macros
result in same value as 0xFFF.
> /*
> * On BDW+ writing LINK_N arms the double buffered update
> * of all the M/N registers, so it must be written last.
> */
> - intel_de_write(i915, link_n_reg, m_n->link_n);
> + intel_de_write(i915, link_n_reg, link_n);
> }
>
> bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
> @@ -3438,7 +3445,13 @@ void intel_get_m_n(struct drm_i915_private
> *i915,
> i915_reg_t link_m_reg, i915_reg_t link_n_reg) {
> m_n->link_m = intel_de_read(i915, link_m_reg) &
> DATA_LINK_M_N_MASK;
> - m_n->link_n = intel_de_read(i915, link_n_reg) &
> DATA_LINK_M_N_MASK;
> + m_n->link_n = intel_de_read(i915, link_n_reg);
> +
> + if (DISPLAY_VER(i915) >= 14)
> + m_n->link_n &= ~PIPE_LINK_N1_EXTENDED_MASK;
> + else
> + m_n->link_n &= DATA_LINK_M_N_MASK;
> +
> m_n->data_m = intel_de_read(i915, data_m_reg) &
> DATA_LINK_M_N_MASK;
> m_n->data_n = intel_de_read(i915, data_n_reg) &
> DATA_LINK_M_N_MASK;
> m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915,
> data_m_reg)) + 1; diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 818142f5a10c..c605642ffc3e
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2167,6 +2167,8 @@
>
> #define _PIPEA_LINK_N1 0x60044
> #define _PIPEB_LINK_N1 0x61044
> +#define PIPE_LINK_N1_EXTENDED_MASK REG_GENMASK(31, 24)
> +#define PIPE_LINK_N1_EXTENDED(val)
> REG_FIELD_PREP(PIPE_LINK_N1_EXTENDED_MASK, (val))
> #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
> _PIPEA_LINK_N1)
>
> #define _PIPEA_LINK_M2 0x60048
> --
> 2.45.2
