[PATCH 2/2] drm/i915/watermark: Modify latency programmed into PKG_C_LATENCY

[Suraj Kandpal]

Increase the latency programmed into PKG_C_LATENCY latency to be
a multiple of line time which is written into WM_LINETIME.

--v2
-Fix commit subject line [Sai Teja]
-Use individual DISPLAY_VER checks instead of range [Sai Teja]
-Initialize max_linetime [Sai Teja]

--v3
-take into account the scenario when adjusted_latency is 0 [Vinod]

--v4
-rename adjusted_latency to latency [Mitul]
-fix the condition in which dpkgc is disabled [Vinod]

--v5
-Add check to see if max_linetime is 0 [Vinod]

WA: 22020299601
Signed-off-by: Suraj Kandpal <suraj.kand...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_wm.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_wm.c 
b/drivers/gpu/drm/i915/display/intel_wm.c
index d893403ff611..c8ba7cc342a4 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.c
+++ b/drivers/gpu/drm/i915/display/intel_wm.c
@@ -157,8 +157,9 @@ intel_program_dpkgc_latency(struct intel_atomic_state 
*state,
        struct intel_display *display = to_intel_display(state);
        struct intel_crtc *crtc;
        struct intel_crtc_state *new_crtc_state;
-       u32 max_latency = LNL_PKG_C_LATENCY_MASK;
+       u32 latency = LNL_PKG_C_LATENCY_MASK;
        u32 added_waketime = 0;
+       u32 max_linetime = 0;
        bool fixed_refresh_rate = false;
        u32 clear, val;
        int i;
@@ -171,18 +172,29 @@ intel_program_dpkgc_latency(struct intel_atomic_state 
*state,
                    (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
                     new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline))
                        fixed_refresh_rate = true;
+
+               max_linetime = max(new_crtc_state->linetime, max_linetime);
        }
 
        if (fixed_refresh_rate) {
-               max_latency = skl_watermark_max_latency(i915, 1);
-               if (max_latency == 0)
-                       max_latency = LNL_PKG_C_LATENCY_MASK;
+               latency = skl_watermark_max_latency(i915, 1);
+
+               /* Wa_22020299601 */
+               if (latency) {
+                       if ((DISPLAY_VER(display) == 20 || DISPLAY_VER(display) 
== 30) &&
+                           max_linetime)
+                               latency = max_linetime *
+                                       DIV_ROUND_UP(latency, max_linetime);
+               } else {
+                       latency = LNL_PKG_C_LATENCY_MASK;
+               }
+
                added_waketime = DSB_EXE_TIME +
                        display->sagv.block_time_us;
        }
 
        clear = LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK;
-       val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency) |
+       val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, latency) |
                REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_waketime);
 
        intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val);
-- 
2.34.1