On Tue, 4 Mar 2014 19:22:54 +0200 Imre Deak <imre.d...@intel.com> wrote:
> Whenever we request a power domain it has to guarantee that all HW > resources are enabled that are needed to access a HW register associated > with that power domain. In case a register is on an always-on power well > this won't result in turning on a power well, but it may require > enabling some other HW resource. One such resource is the HSW/BDW device > D0 state that is required for all register accesses and thus for all > power wells/power domains. > > So far the init power domain (guaranteeing access to all HW registers) > was part of the default i9xx always-on power well, but not the HSW/BDW > always-on power wells. Add the domain to the latter power wells too. > > Atm, all the always-on power wells have noop handlers, so this doesn't > change the functionality. > > v2: > - clarify semantics of always-on power wells (Paulo) > > Signed-off-by: Imre Deak <imre.d...@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ebbd0ed..9a608f1 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5388,7 +5388,8 @@ EXPORT_SYMBOL_GPL(i915_release_power_well); > > #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ > BIT(POWER_DOMAIN_PIPE_A) | \ > - BIT(POWER_DOMAIN_TRANSCODER_EDP)) > + BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ > + BIT(POWER_DOMAIN_INIT)) > #define HSW_DISPLAY_POWER_DOMAINS ( \ > (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ > BIT(POWER_DOMAIN_INIT)) Reviewed-by: Jesse Barnes <jbar...@virtuousgeek.org> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
