On Tue, Jun 04, 2024 at 06:25:24PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the TRANS_VTOTAL register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_crt.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_display.c | 10 +++++-----
> drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++----
> 7 files changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index f87a2170ac91..f95709321ea6 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -953,7 +953,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
> *encoder,
> * struct drm_display_mode.
> * For interlace mode: program required pixel minus 2
> */
> - intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans),
> + intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, dsi_trans),
> VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index 10e95dc425a6..29ab5b112b86 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -708,7 +708,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe
> pipe)
> drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
>
> save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
> - save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
> + save_vtotal = intel_de_read(dev_priv,
> + TRANS_VTOTAL(dev_priv, cpu_transcoder));
> vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
>
> vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 111f2c400ecd..c681a23be1eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2720,7 +2720,7 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
> HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
>
> - intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> + intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
> VACTIVE(crtc_vdisplay - 1) |
> VTOTAL(crtc_vtotal - 1));
> intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> @@ -2736,7 +2736,7 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
> * bits. */
> if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
> (pipe == PIPE_B || pipe == PIPE_C))
> - intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
> + intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, pipe),
> VACTIVE(crtc_vdisplay - 1) |
> VTOTAL(crtc_vtotal - 1));
> }
> @@ -2767,7 +2767,7 @@ static void intel_set_transcoder_timings_lrr(const
> struct intel_crtc_state *crtc
> * The double buffer latch point for TRANS_VTOTAL
> * is the transcoder's undelayed vblank.
> */
> - intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> + intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
> VACTIVE(crtc_vdisplay - 1) |
> VTOTAL(crtc_vtotal - 1));
> }
> @@ -2826,7 +2826,7 @@ static void intel_get_transcoder_timings(struct
> intel_crtc *crtc,
> adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp)
> + 1;
> adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
>
> - tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
> + tmp = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder));
> adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
> adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
>
> @@ -8196,7 +8196,7 @@ void i830_enable_pipe(struct drm_i915_private
> *dev_priv, enum pipe pipe)
> HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
> intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder),
> HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
> - intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> + intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
> VACTIVE(480 - 1) | VTOTAL(525 - 1));
> intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
> b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 480c0e09434d..611a9cd2596f 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -231,7 +231,7 @@ static void ilk_pch_transcoder_set_timings(const struct
> intel_crtc_state *crtc_s
> intel_de_read(dev_priv, TRANS_HSYNC(dev_priv,
> cpu_transcoder)));
>
> intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
> - intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
> + intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv,
> cpu_transcoder)));
> intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
> intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)));
> intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
> b/drivers/gpu/drm/i915/gvt/handlers.c
> index 06ba39b2b103..00cf35a9669e 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -678,7 +678,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu
> *vgpu)
>
> /* Get H/V total from transcoder timing */
> htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >>
> TRANS_HTOTAL_SHIFT);
> - vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(TRANSCODER_A)) >>
> TRANS_VTOTAL_SHIFT);
> + vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(dev_priv, TRANSCODER_A)) >>
> TRANS_VTOTAL_SHIFT);
>
> if (dp_br && link_n && htotal && vtotal) {
> u64 pixel_clk = 0;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0d33815b91a4..3b48022b29a7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1220,7 +1220,7 @@
> #define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
> _TRANS_HTOTAL_A)
> #define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
> _TRANS_HBLANK_A)
> #define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
> _TRANS_HSYNC_A)
> -#define TRANS_VTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
> +#define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans),
> _TRANS_VTOTAL_A)
> #define TRANS_VBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
> #define TRANS_VSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
> #define BCLRPAT(trans) _MMIO_TRANS2(dev_priv, (trans),
> _BCLRPAT_A)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 09d8960f7398..5dd85943e0a1 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -234,7 +234,7 @@ static int iterate_generic_mmio(struct
> intel_gvt_mmio_table_iter *iter)
> MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A));
> MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
> MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
> - MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
> + MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
> MMIO_D(TRANS_VBLANK(TRANSCODER_A));
> MMIO_D(TRANS_VSYNC(TRANSCODER_A));
> MMIO_D(BCLRPAT(TRANSCODER_A));
> @@ -243,7 +243,7 @@ static int iterate_generic_mmio(struct
> intel_gvt_mmio_table_iter *iter)
> MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B));
> MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
> MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
> - MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
> + MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
> MMIO_D(TRANS_VBLANK(TRANSCODER_B));
> MMIO_D(TRANS_VSYNC(TRANSCODER_B));
> MMIO_D(BCLRPAT(TRANSCODER_B));
> @@ -252,7 +252,7 @@ static int iterate_generic_mmio(struct
> intel_gvt_mmio_table_iter *iter)
> MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C));
> MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
> MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
> - MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
> + MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
> MMIO_D(TRANS_VBLANK(TRANSCODER_C));
> MMIO_D(TRANS_VSYNC(TRANSCODER_C));
> MMIO_D(BCLRPAT(TRANSCODER_C));
> @@ -261,7 +261,7 @@ static int iterate_generic_mmio(struct
> intel_gvt_mmio_table_iter *iter)
> MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP));
> MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
> MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
> - MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
> + MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
> MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
> MMIO_D(TRANS_VSYNC(TRANSCODER_EDP));
> MMIO_D(BCLRPAT(TRANSCODER_EDP));
> --
> 2.39.2
>
