On Mon, May 13, 2024 at 08:59:40PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> Now that all pre-skl platforms have their own .min_alignment()
> functions the remainder of intel_surf_alignment() can be hoisted
> into skl_univerals_plane.c (and renamed appropriately).
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fb.c | 77 +------------------
> drivers/gpu/drm/i915/display/intel_fb.h | 4 +-
> .../drm/i915/display/skl_universal_plane.c | 77 ++++++++++++++++++-
> 3 files changed, 78 insertions(+), 80 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> b/drivers/gpu/drm/i915/display/intel_fb.c
> index eea93d84a16e..c80f866f3fb6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -584,7 +584,7 @@ static bool is_gen12_ccs_cc_plane(const struct
> drm_framebuffer *fb, int color_pl
> return intel_fb_rc_ccs_cc_plane(fb) == color_plane;
> }
>
> -static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int
> color_plane)
> +bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int
> color_plane)
> {
> return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
> color_plane == 1;
> @@ -776,81 +776,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
> intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
> }
>
> -unsigned int intel_surf_alignment(struct intel_plane *plane,
> - const struct drm_framebuffer *fb,
> - int color_plane)
> -{
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> -
> - if (intel_fb_uses_dpt(fb)) {
> - /* AUX_DIST needs only 4K alignment */
> - if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> - return 512 * 4096;
> -
> - /*
> - * FIXME ADL sees GGTT/DMAR faults with async
> - * flips unless we align to 16k at least.
> - * Figure out what's going on here...
> - */
> - if (IS_ALDERLAKE_P(dev_priv) &&
> - !intel_fb_is_ccs_modifier(fb->modifier) &&
> - HAS_ASYNC_FLIPS(dev_priv))
> - return 512 * 16 * 1024;
> -
> - return 512 * 4096;
> - }
> -
> - /* AUX_DIST needs only 4K alignment */
> - if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> - return 4096;
> -
> - if (is_semiplanar_uv_plane(fb, color_plane)) {
> - /*
> - * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
> - * alignment for linear UV planes on all platforms.
> - */
> - if (DISPLAY_VER(dev_priv) >= 12) {
> - if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> - return 256 * 1024;
> -
> - return intel_tile_row_size(fb, color_plane);
> - }
> -
> - return 4096;
> - }
> -
> - drm_WARN_ON(&dev_priv->drm, color_plane != 0);
> -
> - switch (fb->modifier) {
> - case DRM_FORMAT_MOD_LINEAR:
> - return 256 * 1024;
> - case I915_FORMAT_MOD_X_TILED:
> - if (HAS_ASYNC_FLIPS(dev_priv))
> - return 256 * 1024;
> - return 0;
> - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> - case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
> - case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
> - case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
> - return 16 * 1024;
> - case I915_FORMAT_MOD_Y_TILED_CCS:
> - case I915_FORMAT_MOD_Yf_TILED_CCS:
> - case I915_FORMAT_MOD_Y_TILED:
> - case I915_FORMAT_MOD_4_TILED:
> - case I915_FORMAT_MOD_Yf_TILED:
> - return 1 * 1024 * 1024;
> - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> - case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> - return 16 * 1024;
> - default:
> - MISSING_CASE(fb->modifier);
> - return 0;
> - }
> -}
> -
> void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
> const struct drm_framebuffer *fb,
> int color_plane)
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
> b/drivers/gpu/drm/i915/display/intel_fb.h
> index 16ebb573643f..1b1fef2dc39a 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.h
> +++ b/drivers/gpu/drm/i915/display/intel_fb.h
> @@ -34,6 +34,7 @@ bool intel_fb_is_ccs_modifier(u64 modifier);
> bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
> bool intel_fb_is_mc_ccs_modifier(u64 modifier);
>
> +bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int
> color_plane);
> bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int
> color_plane);
> int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
>
> @@ -60,9 +61,6 @@ unsigned int intel_tile_height(const struct drm_framebuffer
> *fb, int color_plane
> unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int
> color_plane);
> unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
> int color_plane, unsigned int height);
> -unsigned int intel_surf_alignment(struct intel_plane *plane,
> - const struct drm_framebuffer *fb,
> - int color_plane);
>
> void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
> const struct drm_framebuffer *fb,
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 27782f5060ad..1ecd7c691317 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -502,6 +502,81 @@ skl_plane_max_stride(struct intel_plane *plane,
> max_pixels, max_bytes);
> }
>
> +static unsigned int skl_plane_min_alignment(struct intel_plane *plane,
> + const struct drm_framebuffer *fb,
> + int color_plane)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +
> + if (intel_fb_uses_dpt(fb)) {
> + /* AUX_DIST needs only 4K alignment */
> + if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> + return 512 * 4096;
> +
> + /*
> + * FIXME ADL sees GGTT/DMAR faults with async
> + * flips unless we align to 16k at least.
> + * Figure out what's going on here...
> + */
> + if (IS_ALDERLAKE_P(dev_priv) &&
> + !intel_fb_is_ccs_modifier(fb->modifier) &&
> + HAS_ASYNC_FLIPS(dev_priv))
> + return 512 * 16 * 1024;
> +
> + return 512 * 4096;
> + }
> +
> + /* AUX_DIST needs only 4K alignment */
> + if (intel_fb_is_ccs_aux_plane(fb, color_plane))
> + return 4096;
> +
> + if (is_semiplanar_uv_plane(fb, color_plane)) {
> + /*
> + * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
> + * alignment for linear UV planes on all platforms.
> + */
> + if (DISPLAY_VER(dev_priv) >= 12) {
> + if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> + return 256 * 1024;
> +
> + return intel_tile_row_size(fb, color_plane);
> + }
> +
> + return 4096;
> + }
> +
> + drm_WARN_ON(&dev_priv->drm, color_plane != 0);
> +
> + switch (fb->modifier) {
> + case DRM_FORMAT_MOD_LINEAR:
> + return 256 * 1024;
> + case I915_FORMAT_MOD_X_TILED:
> + if (HAS_ASYNC_FLIPS(dev_priv))
> + return 256 * 1024;
> + return 0;
> + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
> + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
> + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
> + return 16 * 1024;
> + case I915_FORMAT_MOD_Y_TILED_CCS:
> + case I915_FORMAT_MOD_Yf_TILED_CCS:
> + case I915_FORMAT_MOD_Y_TILED:
> + case I915_FORMAT_MOD_4_TILED:
> + case I915_FORMAT_MOD_Yf_TILED:
> + return 1 * 1024 * 1024;
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> + return 16 * 1024;
> + default:
> + MISSING_CASE(fb->modifier);
> + return 0;
> + }
> +}
> +
> /* Preoffset values for YUV to RGB Conversion */
> #define PREOFF_YUV_TO_RGB_HI 0x1800
> #define PREOFF_YUV_TO_RGB_ME 0x0000
> @@ -2367,7 +2442,7 @@ skl_universal_plane_create(struct drm_i915_private
> *dev_priv,
> else
> plane->max_stride = skl_plane_max_stride;
>
> - plane->min_alignment = intel_surf_alignment;
> + plane->min_alignment = skl_plane_min_alignment;
>
> if (DISPLAY_VER(dev_priv) >= 11) {
> plane->update_noarm = icl_plane_update_noarm;
> --
> 2.43.2
>
