On Fri, 2014-02-21 at 13:52 -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zan...@intel.com>
>
> Otherwise, when we run intel_modeset_check_state we may already be
> runtime suspended, and our state checking code will read registers
> while the device is suspended. This can only happen if your
> autosuspend_delay_ms is low (not the default 10s).
>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 10ec401..c64fb7f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9746,13 +9746,18 @@ static int intel_set_mode(struct drm_crtc *crtc,
> struct drm_display_mode *mode,
> int x, int y, struct drm_framebuffer *fb)
> {
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> int ret;
>
> + intel_runtime_pm_get(dev_priv);
> +
> ret = __intel_set_mode(crtc, mode, x, y, fb);
>
> if (ret == 0)
> intel_modeset_check_state(crtc->dev);
>
> + intel_runtime_pm_put(dev_priv);
> return ret;
> }Ideally these should be done as part of a power domain get/put as some platforms will need to turn on some power wells too and on that path we do anyway a runtime PM get/put. In the latest VLV power domain support patchset [1] I added the power domain get/put and state check to places I thought necessary. I haven't tested it on HSW but afaics the ones added for the HW state readout code would solve the issue you describe here. --Imre [1] http://www.spinics.net/lists/intel-gfx/msg40344.html
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