[PATCH v3 07/21] drm/i915/psr: Do not write registers/bits not applicable for panel replay

[Jouni Högander]

>From bspec:

Additional programming considerations (repurposed eDP registers)

mask register: Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug]
are used in panel replay mode.

Status register: Only SRD_STATUS[SRD state] field is used in panel replay
mode.

Due to this stop writing and reading registers and bits not used by panel
replay if panel replay is used.

Bspec: 53370

Signed-off-by: Jouni Högander <jouni.hogan...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 6d7ef74201d2..2d5d1c2ce246 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -346,6 +346,9 @@ static void psr_irq_control(struct intel_dp *intel_dp)
        enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
        u32 mask;
 
+       if (intel_dp->psr.panel_replay_enabled)
+               return;
+
        mask = psr_irq_psr_error_bit_get(intel_dp);
        if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
                mask |= psr_irq_post_exit_bit_get(intel_dp) |
@@ -1559,13 +1562,19 @@ static void intel_psr_enable_source(struct intel_dp 
*intel_dp,
         * mask LPSP to avoid dependency on other drivers that might block
         * runtime_pm besides preventing  other hw tracking issues now we
         * can rely on frontbuffer tracking.
+        *
+        * From bspec: Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug]
+        * are used in panel replay mode.
         */
-       mask = EDP_PSR_DEBUG_MASK_MEMUP |
-              EDP_PSR_DEBUG_MASK_HPD |
-              EDP_PSR_DEBUG_MASK_LPSP;
+       mask = EDP_PSR_DEBUG_MASK_HPD;
 
-       if (DISPLAY_VER(dev_priv) < 20)
-               mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+       if (!intel_dp->psr.panel_replay_enabled) {
+               mask |= EDP_PSR_DEBUG_MASK_MEMUP |
+                       EDP_PSR_DEBUG_MASK_LPSP;
+
+               if (DISPLAY_VER(dev_priv) < 20)
+                       mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+       }
 
        /*
         * No separate pipe reg write mask on hsw/bdw, so have to unmask all
@@ -1634,6 +1643,9 @@ static bool psr_interrupt_error_check(struct intel_dp 
*intel_dp)
        enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
        u32 val;
 
+       if (intel_dp->psr.panel_replay_enabled)
+               goto no_err;
+
        /*
         * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
         * will still keep the error set even after the reset done in the
@@ -1651,6 +1663,7 @@ static bool psr_interrupt_error_check(struct intel_dp 
*intel_dp)
                return false;
        }
 
+no_err:
        return true;
 }
 
-- 
2.34.1