On Fri, Sep 22, 2023 at 09:23:56PM +0530, Shekhar Chauhan wrote:
> Drop UGM per set fragment threshold to 3
>
> BSpec: 54833
> Signed-off-by: Shekhar Chauhan <shekhar.chau...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index a00ff51c681d..431c575c532b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1230,6 +1230,7 @@
> #define DISABLE_D8_D16_COASLESCE REG_BIT(30)
> #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
> #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4)
> +#define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32)
> #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
> #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
> #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 660d4f358eab..df0fba2850b6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2957,6 +2957,11 @@ general_render_compute_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_li
> wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
> }
> +
> + if (IS_DG2_G10(i915) || IS_DG2_G12(i915)) {
> + /* Wa_18028616096 */
> + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
> UGM_FRAGMENT_THRESHOLD_TO_3);
> + }
It might be best to move this block above the xehpsdv block (to keep the
function roughly ordered by "newest platforms first"). But we can do
that while applying the patch; no need to send another version.
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
> }
>
> static void
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
