> Subject: [PATCH 8/8] drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends
> for PPS0 and PPS1
>
> Use the register helper macros for PPS0 and PPS1 register contents.
>
LGTM.
Reviewed-by: Suraj Kandpal <suraj.kand...@intel.com>
> Cc: Suraj Kandpal <suraj.kand...@intel.com>
> Cc: Ankit Nautiyal <ankit.k.nauti...@intel.com>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 15 +++++------
> .../gpu/drm/i915/display/intel_vdsc_regs.h | 27 ++++++++++---------
> 2 files changed, 22 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 126aff804e33..5c00f7ccad7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -423,10 +423,10 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
> int vdsc_instances_per_pipe =
> intel_dsc_get_vdsc_per_pipe(crtc_state);
>
> /* PPS 0 */
> - pps_val = DSC_PPS0_VER_MAJ | vdsc_cfg->dsc_version_minor <<
> - DSC_PPS0_VER_MIN_SHIFT |
> - vdsc_cfg->bits_per_component << DSC_PPS0_BPC_SHIFT |
> - vdsc_cfg->line_buf_depth <<
> DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
> + pps_val = DSC_PPS0_VER_MAJOR(1) |
> + DSC_PPS0_VER_MINOR(vdsc_cfg->dsc_version_minor) |
> + DSC_PPS0_BPC(vdsc_cfg->bits_per_component) |
> + DSC_PPS0_LINE_BUF_DEPTH(vdsc_cfg->line_buf_depth);
> if (vdsc_cfg->dsc_version_minor == 2) {
> pps_val |= DSC_PPS0_ALT_ICH_SEL;
> if (vdsc_cfg->native_420)
> @@ -857,9 +857,8 @@ static void intel_dsc_get_pps_config(struct
> intel_crtc_state *crtc_state)
> /* PPS 0 */
> pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
>
> - vdsc_cfg->bits_per_component = (pps_temp & DSC_PPS0_BPC_MASK)
> >> DSC_PPS0_BPC_SHIFT;
> - vdsc_cfg->line_buf_depth =
> - (pps_temp & DSC_PPS0_LINE_BUF_DEPTH_MASK) >>
> DSC_PPS0_LINE_BUF_DEPTH_SHIFT;
> + vdsc_cfg->bits_per_component =
> REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp);
> + vdsc_cfg->line_buf_depth =
> REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK,
> +pps_temp);
> vdsc_cfg->block_pred_enable = pps_temp &
> DSC_PPS0_BLOCK_PREDICTION;
> vdsc_cfg->convert_rgb = pps_temp &
> DSC_PPS0_COLOR_SPACE_CONVERSION;
> vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE; @@ -
> 870,7 +869,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state
> *crtc_state)
> /* PPS 1 */
> pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
>
> - vdsc_cfg->bits_per_pixel = pps_temp;
> + vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK,
> pps_temp);
>
> if (vdsc_cfg->native_420)
> vdsc_cfg->bits_per_pixel >>= 1;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> index 92782de2b309..64f440fdc22b 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> @@ -73,22 +73,25 @@
> #define ICL_DSC1_PPS(pipe, pps)
> _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
>
> /* PPS 0 */
> -#define DSC_PPS0_NATIVE_422_ENABLE BIT(23)
> -#define DSC_PPS0_NATIVE_420_ENABLE BIT(22)
> -#define DSC_PPS0_ALT_ICH_SEL (1 << 20)
> -#define DSC_PPS0_VBR_ENABLE (1 << 19)
> -#define DSC_PPS0_422_ENABLE (1 << 18)
> -#define DSC_PPS0_COLOR_SPACE_CONVERSION (1 << 17)
> -#define DSC_PPS0_BLOCK_PREDICTION (1 << 16)
> -#define DSC_PPS0_LINE_BUF_DEPTH_SHIFT 12
> +#define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23)
> +#define DSC_PPS0_NATIVE_420_ENABLE REG_BIT(22)
> +#define DSC_PPS0_ALT_ICH_SEL REG_BIT(20)
> +#define DSC_PPS0_VBR_ENABLE REG_BIT(19)
> +#define DSC_PPS0_422_ENABLE REG_BIT(18)
> +#define DSC_PPS0_COLOR_SPACE_CONVERSION REG_BIT(17)
> +#define DSC_PPS0_BLOCK_PREDICTION REG_BIT(16)
> #define DSC_PPS0_LINE_BUF_DEPTH_MASK REG_GENMASK(15,
> 12)
> -#define DSC_PPS0_BPC_SHIFT 8
> +#define DSC_PPS0_LINE_BUF_DEPTH(depth)
> REG_FIELD_PREP(DSC_PPS0_LINE_BUF_DEPTH_MASK, depth)
> #define DSC_PPS0_BPC_MASK REG_GENMASK(11, 8)
> -#define DSC_PPS0_VER_MIN_SHIFT 4
> -#define DSC_PPS0_VER_MAJ (0x1 << 0)
> +#define DSC_PPS0_BPC(bpc)
> REG_FIELD_PREP(DSC_PPS0_BPC_MASK, bpc)
> +#define DSC_PPS0_VER_MINOR_MASK REG_GENMASK(7, 4)
> +#define DSC_PPS0_VER_MINOR(minor)
> REG_FIELD_PREP(DSC_PPS0_VER_MINOR_MASK, minor)
> +#define DSC_PPS0_VER_MAJOR_MASK REG_GENMASK(3, 0)
> +#define DSC_PPS0_VER_MAJOR(major)
> REG_FIELD_PREP(DSC_PPS0_VER_MAJOR_MASK, major)
>
> /* PPS 1 */
> -#define DSC_PPS1_BPP(bpp) ((bpp) << 0)
> +#define DSC_PPS1_BPP_MASK REG_GENMASK(9, 0)
> +#define DSC_PPS1_BPP(bpp)
> REG_FIELD_PREP(DSC_PPS1_BPP_MASK, bpp)
>
> /* PPS 2 */
> #define DSC_PPS2_PIC_WIDTH_MASK REG_GENMASK(31, 16)
> --
> 2.39.2
