From: Jeff McGee <jeff.mc...@intel.com>
i915_rc6_disable:
'0' - RC6 states used normally per device and settings.
'1' - RC6 states explicitly disabled.
Supports Gen6+ except Valleyview and Broadwell.
Signed-off-by: Jeff McGee <jeff.mc...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 49 +++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 5 ++++
drivers/gpu/drm/i915/intel_pm.c | 31 ++++++++++++++++++++---
3 files changed, 81 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index c6d4da0..a51c357 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3431,6 +3431,54 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_rps_manual_fops,
i915_rps_manual_get, i915_rps_manual_set,
"%llu\n");
+static int i915_rc6_disable_get(void *data, u64 *val)
+{
+ struct drm_device *dev = data;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+ if ((INTEL_INFO(dev)->gen < 6) ||
+ IS_VALLEYVIEW(dev) ||
+ IS_BROADWELL(dev))
+ return -ENODEV;
+
+ flush_delayed_work(&dev_priv->rps.delayed_resume_work);
+
+ *val = dev_priv->rps.rc6_disable;
+
+ return 0;
+}
+
+static int i915_rc6_disable_set(void *data, u64 val)
+{
+ struct drm_device *dev = data;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int ret;
+
+ if ((INTEL_INFO(dev)->gen < 6) ||
+ IS_VALLEYVIEW(dev) ||
+ IS_BROADWELL(dev))
+ return -ENODEV;
+
+ flush_delayed_work(&dev_priv->rps.delayed_resume_work);
+
+ DRM_DEBUG_DRIVER("Setting RC6 disable %s\n",
+ val ? "true" : "false");
+
+ ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
+ if (ret)
+ return ret;
+
+ gen6_set_rc6_mode(dev, val);
+
+ mutex_unlock(&dev_priv->rps.hw_lock);
+
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_rc6_disable_fops,
+ i915_rc6_disable_get, i915_rc6_disable_set,
+ "%llu\n");
+
static int
i915_cache_sharing_get(void *data, u64 *val)
{
@@ -3607,6 +3655,7 @@ static const struct i915_debugfs_files {
{"i915_min_freq", &i915_min_freq_fops},
{"i915_cur_freq", &i915_cur_freq_fops},
{"i915_rps_manual", &i915_rps_manual_fops},
+ {"i915_rc6_disable", &i915_rc6_disable_fops},
{"i915_cache_sharing", &i915_cache_sharing_fops},
{"i915_ring_stop", &i915_ring_stop_fops},
{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 73fd646..9893451 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -970,6 +970,10 @@ struct intel_gen6_power_mgmt {
bool manual_mode;
bool enabled;
+
+ u32 rc6_mask;
+ bool rc6_disable;
+
struct delayed_work delayed_resume_work;
/*
@@ -2537,6 +2541,7 @@ extern bool intel_fbc_enabled(struct drm_device *dev);
extern void intel_disable_fbc(struct drm_device *dev);
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
extern void intel_init_pch_refclk(struct drm_device *dev);
+extern void gen6_set_rc6_mode(struct drm_device *dev, bool disable);
extern void gen6_set_rps_mode(struct drm_device *dev, bool manual);
extern void gen6_set_rps(struct drm_device *dev, u8 val);
extern void valleyview_set_rps(struct drm_device *dev, u8 val);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cfdf5f0..6478116 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3071,6 +3071,30 @@ void gen6_set_rps_mode(struct drm_device *dev, bool
manual)
gen6_set_rps(dev, delay);
}
+void gen6_set_rc6_mode(struct drm_device *dev, bool disable)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if ((INTEL_INFO(dev)->gen < 6) ||
+ IS_VALLEYVIEW(dev) ||
+ IS_BROADWELL(dev)) {
+ DRM_DEBUG_DRIVER("RC6 disable not supported\n");
+ return;
+ }
+
+ WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+ dev_priv->rps.rc6_disable = disable;
+
+ if (disable)
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+ else
+ I915_WRITE(GEN6_RC_CONTROL,
+ dev_priv->rps.rc6_mask |
+ GEN6_RC_CTL_EI_MODE(1) |
+ GEN6_RC_CTL_HW_ENABLE);
+}
+
void gen6_rps_idle(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
@@ -3376,10 +3400,9 @@ static void gen6_enable_rps(struct drm_device *dev)
intel_print_rc6_info(dev, rc6_mask);
- I915_WRITE(GEN6_RC_CONTROL,
- rc6_mask |
- GEN6_RC_CTL_EI_MODE(1) |
- GEN6_RC_CTL_HW_ENABLE);
+ dev_priv->rps.rc6_mask = rc6_mask;
+
+ gen6_set_rc6_mode(dev, dev_priv->rps.rc6_disable);
/* Power down if completely idle for over 50ms */
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
--
1.8.5.2
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