On Thu, Jan 30, 2014 at 04:52:24PM +0100, Daniel Vetter wrote: > On Thu, Jan 30, 2014 at 04:50:42PM +0200, Imre Deak wrote: > > Atm we setup the HW panel power sequencer logic both for eDP and DP > > ports. On eDP we then go on and start the power on sequence and commence > > with link training when it's ready. On DP we don't do the power on > > sequencing but do the link training immediately. At this point the DP > > PHY block gets stuck, since - supposedly - it is waiting for the power > > on sequence to finish. The actual register write that seems to hold off > > the PHY is PIPEX_PP_ON_DELAYS[Panel Control Port Select]. Writing here > > a non-0 value eventually sets PIPEX_PP_STATUS[Require Asset Status] to > > 1 and blocks the PHY until the panel power on is ready. > > > > Fix this by not doing any PP sequencing setup for DP ports. > > > > Thanks to Ville Syrjälä, Jesse Barnes and Todd Previte for the help in > > tracking this down. > > > > Signed-off-by: Imre Deak <imre.d...@intel.com> > > Ah, the infamous ABCD hack we're using all over the place in intel_lvds.c. > On edp we didn't have a need for it thus far since the "require asset > status" checks have all been fused of, with the PP being on the PCH and > the edp port on the north display block. If this is really all we need to > appease the hardware then I'm heavily in favour of it as opposed to > resurrect the ABCD hack for intel_dp.c. > > One thing though: Should we add a check for the "Required Asset Status" > bit somewhere? I don't really have a good idea for a spot to put this > into, hence the question.
Also: Picked up for -fixes, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
