[Intel-gfx] [PATCH 07/13] drm/i915: Add register whitelist for DRM master

[bradley . d . volkin]

From: Brad Volkin <bradley.d.vol...@intel.com>

These are used to implement scanline waits in the X server.

Signed-off-by: Brad Volkin <bradley.d.vol...@intel.com>
---
 drivers/gpu/drm/i915/i915_cmd_parser.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c 
b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 18d5b05..296e322 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -234,6 +234,20 @@ static const u32 gen7_blt_regs[] = {
        BCS_SWCTRL,
 };
 
+/* Whitelists for the DRM master. Magic numbers are taken from sna, to match. 
*/
+static const u32 ivb_master_regs[] = {
+       0xa188, /* FORCEWAKE_MT */
+       0x44050, /* DERRMR */
+       0x70068,
+       0x71068,
+       0x72068,
+};
+
+static const u32 hsw_master_regs[] = {
+       0xa188, /* FORCEWAKE_MT */
+       0x44050, /* DERRMR */
+};
+
 #define CLIENT_MASK      0xE0000000
 #define SUBCLIENT_MASK   0x18000000
 #define MI_CLIENT        0x00000000
@@ -365,6 +379,14 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer 
*ring)
                ring->reg_table = gen7_render_regs;
                ring->reg_count = ARRAY_SIZE(gen7_render_regs);
 
+               if (IS_HASWELL(ring->dev)) {
+                       ring->master_reg_table = hsw_master_regs;
+                       ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
+               } else {
+                       ring->master_reg_table = ivb_master_regs;
+                       ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
+               }
+
                ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
                break;
        case VCS:
@@ -384,6 +406,14 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer 
*ring)
                ring->reg_table = gen7_blt_regs;
                ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
 
+               if (IS_HASWELL(ring->dev)) {
+                       ring->master_reg_table = hsw_master_regs;
+                       ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
+               } else {
+                       ring->master_reg_table = ivb_master_regs;
+                       ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
+               }
+
                ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
                break;
        case VECS:
-- 
1.8.5.2

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