On Mon, Jan 27, 2014 at 02:20:16PM -0800, Kenneth Graunke wrote:
> On Broadwell, any PIPE_CONTROL with the "State Cache Invalidate" bit set
> must be preceded by a PIPE_CONTROL with the "CS Stall" bit set.
>
> Documented on the BSpec 3D workarounds page.
FWIW, I am not clear this is actually needed. If it is, we need/should
file a bspec bug, since it is missing there. What I am afraid happened
is Windows carried it over from gen7, and that's how it ended up in the
w/a db.
As I am too lazy to check the performance implications (or whether it's
really needed) - I say just ship it.
>
> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> The Gen7 code doesn't check ret on the state cache workaround, but it
> seems like we ought to.
>
> At this point, gen7_render_ring_flush and gen8_render_ring_flush look
> pretty darn similar. We could probably merge them, if people are
> interested in that...
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 4774bfa..049b019 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -389,6 +389,7 @@ gen8_render_ring_flush(struct intel_ring_buffer *ring,
> {
> u32 flags = 0;
> u32 scratch_addr = ring->scratch.gtt_offset + 128;
> + int ret;
>
> /* For CS stalls, one of the following must also be set:
> * - Render Target Cache Flush
> @@ -412,6 +413,14 @@ gen8_render_ring_flush(struct intel_ring_buffer *ring,
> flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
> flags |= PIPE_CONTROL_QW_WRITE;
> flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> +
> + /* WaCsStallBeforeStateCacheInvalidate:bdw */
> + ret = gen8_emit_pipe_control(ring,
> + PIPE_CONTROL_CS_STALL |
> + PIPE_CONTROL_STALL_AT_SCOREBOARD,
> + 0);
> + if (ret)
> + return ret;
> }
>
> return gen8_emit_pipe_control(ring, flags, scratch_addr);
> --
> 1.8.5.2
>
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--
Ben Widawsky, Intel Open Source Technology Center
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