[Intel-gfx] [PATCH 2/2] drm/i915/dp: Add TPS4 PHY test pattern support

[Khaled Almahallawy]

Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests.

Bspec: 50482, 50484

CC: Jani Nikula <jani.nik...@intel.com>
Cc: Imre Deak <imre.d...@intel.com>
Cc: Lee Shawn C <shawn.c....@intel.com>
Signed-off-by: Khaled Almahallawy <khaled.almahall...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++++++++
 drivers/gpu/drm/i915/i915_reg.h         |  4 ++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 08b607288a6a..5c6601a71f4a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3878,6 +3878,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp 
*intel_dp,
        struct drm_dp_phy_test_params *data =
                        &intel_dp->compliance.test_data.phytest;
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
        enum pipe pipe = crtc->pipe;
        u32 pattern_val;
 
@@ -3885,6 +3886,9 @@ static void intel_dp_phy_pattern_update(struct intel_dp 
*intel_dp,
        case DP_LINK_QUAL_PATTERN_DISABLE:
                drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
                intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+               intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
+                            DP_TP_CTL_TRAIN_PAT4_SEL_MASK | 
DP_TP_CTL_LINK_TRAIN_MASK,
+                            DP_TP_CTL_LINK_TRAIN_NORMAL);
                break;
        case DP_LINK_QUAL_PATTERN_D10_2:
                drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
@@ -3932,6 +3936,13 @@ static void intel_dp_phy_pattern_update(struct intel_dp 
*intel_dp,
                               DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
                               pattern_val);
                break;
+       case DP_LINK_QUAL_PATTERN_CP2520_PAT_3:
+               drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test 
Pattern\n");
+               intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+               intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
+                            DP_TP_CTL_TRAIN_PAT4_SEL_MASK | 
DP_TP_CTL_LINK_TRAIN_MASK,
+                            DP_TP_CTL_TRAIN_PAT4_SEL_TP4a | 
DP_TP_CTL_LINK_TRAIN_PAT4);
+               break;
        default:
                WARN(1, "Invalid Phy Test Pattern\n");
        }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2a9ab8de8421..64cdf9b31ca8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5676,6 +5676,10 @@ enum skl_power_gate {
 #define  DP_TP_CTL_MODE_SST                    (0 << 27)
 #define  DP_TP_CTL_MODE_MST                    (1 << 27)
 #define  DP_TP_CTL_FORCE_ACT                   (1 << 25)
+#define  DP_TP_CTL_TRAIN_PAT4_SEL_MASK         (3 << 19)
+#define  DP_TP_CTL_TRAIN_PAT4_SEL_TP4a         (0 << 19)
+#define  DP_TP_CTL_TRAIN_PAT4_SEL_TP4b         (1 << 19)
+#define  DP_TP_CTL_TRAIN_PAT4_SEL_TP4c         (2 << 19)
 #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE       (1 << 18)
 #define  DP_TP_CTL_FDI_AUTOTRAIN               (1 << 15)
 #define  DP_TP_CTL_LINK_TRAIN_MASK             (7 << 8)
-- 
2.34.1