On Thu, Jan 23, 2014 at 05:19:19PM -0200, Rodrigo Vivi wrote: > This patch allows system to safely recover after kms_psr_sink_crc check > or any other similar case that might fail when PSR is enabled. > > Ville made and sent me this patch after noticing that primary plane enabled > bit was set during test case and unset after failure. What was causing a hard > and non-recoverable blank screen. > > After the failure when alternating from fbcon to x section it was possible to > see and move mouse cursor, but nothing else. Everything else was fully black. > A for dpms off/on also haleped to get screen back. But this patch seeting > primary plane enabled bit propertly seemed more clean. > > v2: Fix identation issue. > > Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.v...@gmail.com> > --- > drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index dde98020..ed5ffce 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2095,6 +2095,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, > struct drm_framebuffer *fb, > if (IS_G4X(dev)) > dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; > > + if (intel_crtc->primary_enabled) > + dspcntr |= DISPLAY_PLANE_ENABLE; > + > I915_WRITE(reg, dspcntr); > > linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); > @@ -2192,6 +2195,9 @@ static int ironlake_update_plane(struct drm_crtc *crtc, > else > dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; > > + if (intel_crtc->primary_enabled) > + dspcntr |= DISPLAY_PLANE_ENABLE; > + > I915_WRITE(reg, dspcntr); > > linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); > @@ -8586,6 +8592,11 @@ static int intel_gen7_queue_flip(struct drm_device > *dev, > intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + > intel_crtc->dspaddr_offset); > intel_ring_emit(ring, (MI_NOOP)); > > + if (IS_VALLEYVIEW(dev) && intel_crtc->primary_enabled) > + I915_WRITE(DSPCNTR(intel_crtc->plane), > + I915_READ(DSPCNTR(intel_crtc->plane)) > + | DISPLAY_PLANE_ENABLE);
We should add some kind of big comment that this ugly hack is here for PSR. I assume we're going to remove it eventually once someone figures out why the port/pipe/PLL aren't shutting down during PSR. To wake the hardware back from that state takes a lot more than just flipping a plane enable bit. > + > intel_mark_page_flip_active(intel_crtc); > __intel_ring_advance(ring); > return 0; > -- > 1.8.1.2 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
