== Series Details == Series: drm/i915/mtl: Add support for C20 phy (rev2) URL : https://patchwork.freedesktop.org/series/116755/ State : success
== Summary == CI Bug Log - changes from CI_DRM_13073 -> Patchwork_116755v2 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v2/index.html Participating hosts (39 -> 37) ------------------------------ Missing (2): fi-kbl-soraka fi-snb-2520m Known issues ------------ Here are the changes found in Patchwork_116755v2 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live@reset: - bat-rpls-1: [PASS][1] -> [ABORT][2] ([i915#4983] / [i915#7461] / [i915#8384]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13073/bat-rpls-1/igt@i915_selftest@l...@reset.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v2/bat-rpls-1/igt@i915_selftest@l...@reset.html * igt@i915_selftest@live@slpc: - bat-adln-1: NOTRUN -> [DMESG-FAIL][3] ([i915#6997]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v2/bat-adln-1/igt@i915_selftest@l...@slpc.html * igt@kms_chamelium_hpd@common-hpd-after-suspend: - bat-adln-1: NOTRUN -> [SKIP][4] ([i915#7828]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v2/bat-adln-1/igt@kms_chamelium_...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1: - bat-dg2-8: [PASS][5] -> [FAIL][6] ([i915#7932]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13073/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-seque...@pipe-d-dp-1.html #### Possible fixes #### * igt@i915_selftest@live@gt_lrc: - bat-adln-1: [INCOMPLETE][7] ([i915#4983] / [i915#7609]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13073/bat-adln-1/igt@i915_selftest@live@gt_lrc.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v2/bat-adln-1/igt@i915_selftest@live@gt_lrc.html * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1: - bat-dg2-8: [FAIL][9] ([i915#7932]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13073/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v2/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-...@pipe-d-dp-1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997 [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461 [i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920 [i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932 [i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384 Build changes ------------- * Linux: CI_DRM_13073 -> Patchwork_116755v2 CI-20190529: 20190529 CI_DRM_13073: d4602c57ac02d66526e4785b80c2e01dea122f33 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7275: c284bd66d7b416b4eaca456d6085b9180ad58058 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_116755v2: d4602c57ac02d66526e4785b80c2e01dea122f33 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits cfe10aa9f670 drm/i915/mtl: Enable TC ports a76a271e840c drm/i915/mtl: Pin assignment for TypeC af5b94a2f2cb drm/i915/mtl: TypeC HPD live status query 73e409d6e8e9 drm/i915/mtl: Power up TCSS 89031c1f2c58 drm/i915/mtl: Define mask for DDI AUX interrupts 01f19c8138fa drm/i915/mtl: Readout Thunderbolt HW state 6a8a44923092 drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll ed0bd3453efe drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA ecd48801a943 drm/i915/mtl: Add voltage swing sequence for C20 5777f9bceb6a drm/i915/mtl: C20 port clock calculation 357247eb8025 drm/i915/mtl: Dump C20 pll hw state dc0e2e2381d3 drm/i915/mtl: C20 HW readout 39ba77b93b8f drm/i915/mtl: C20 PLL programming == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116755v2/index.html
