On Thu, Feb 23, 2023 at 05:25:09PM +0530, Ankit Nautiyal wrote: > While computing compressed bpp, maximum value of bits_per_pixel is > calculated that can be supported with the given link configuration > for a given mode. Avoid rounding up of this max bits_per_pixel. > Also improve documentation for computing max bits_per_pixel. > > Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index b77bd4565864..51e9d0b2d8b3 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -716,9 +716,19 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private > *i915, > * (LinkSymbolClock)* 8 * (TimeSlots / 64) > * for SST -> TimeSlots is 64(i.e all TimeSlots that are available) > * for MST -> TimeSlots has to be calculated, based on mode requirements > + * > + * Due to FEC overhead, the available bw is reduced to 97.2261%. > + * To support the given mode: > + * Bandwidth required should be <= Available link Bandwidth * FEC > Overhead > + * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC > Overhead > + * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / > ModeClock > + * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots > / 64) / > + * (ModeClock / FEC Overhead) > + * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) / > + * (ModeClock / FEC Overhead * 8) > */ > - bits_per_pixel = DIV_ROUND_UP((link_clock * lane_count) * timeslots, > - intel_dp_mode_to_fec_clock(mode_clock) * > 8); > + bits_per_pixel = ((link_clock * lane_count) * timeslots) / > + (intel_dp_mode_to_fec_clock(mode_clock) * 8); > > drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots " > "total bw %u pixel clock %u\n", > -- > 2.25.1 >
