On Mon, 2023-01-30 at 10:06 +0200, Jouni Högander wrote: > SEL_FETCH_CTL registers are armed immediately when plane is disabled. > SEL_FETCH_* instances of plane configuration are used when doing > selective update and normal plane register instances for full updates. > Currently all SEL_FETCH_* registers are written as a part of noarm > plane configuration. If noarm and arm plane configuration are not > happening within same vblank we may end up having plane as a part of > selective update before it's PLANE_SURF register is written. > > Fix this by splitting plane selective fetch configuration into arm and > noarm versions and call them accordingly. Write SEL_FETCH_CTL in arm > version. > > v3: > - add arm suffix into intel_psr2_disable_plane_sel_fetch > v2: > - drop color_plane parameter from arm part > - dev_priv -> i915 in arm part > > Cc: Ville Syrjälä <ville.syrj...@linux.intel.com> > Cc: José Roberto de Souza <jose.so...@intel.com> > Cc: Mika Kahola <mika.kah...@intel.com> > Cc: Vinod Govindapillai <vinod.govindapil...@intel.com> > Cc: Stanislav Lisovskiy <stanislav.lisovs...@intel.com> > Cc: Luca Coelho <luciano.coe...@intel.com> > Signed-off-by: Jouni Högander <jouni.hogan...@intel.com> > Reviewed-by: José Roberto de Souza <jose.so...@intel.com> > ---
Reviewed-by: Luca Coelho <luciano.coe...@intel.com> -- Cheers, Luca.
