On Tue, 10 Jan 2023, Matt Roper <matthew.d.ro...@intel.com> wrote: > On Tue, Jan 10, 2023 at 11:06:14AM +0200, Jani Nikula wrote: >> On Sat, 07 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.bo...@intel.com> >> wrote: >> > @@ -3353,6 +3374,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private >> > *dev_priv) >> > /* Wa_22011320316:adl-p[a0] */ >> > if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) >> > dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; >> >> Are RPL-U A0-B0 going to enter this branch? Is this the right thing to >> do? > > There's no such thing as a RPL A0/B0. RPL continues the stepping > progression from ADL, and all RPL parts have E0 or newer display > steppings (bspec 55376).
Ok, thanks. -- Jani Nikula, Intel Open Source Graphics Center
