On Wed, 30 Nov 2022, Chaitanya Kumar Borah <chaitanya.kumar.bo...@intel.com>
wrote:
> A new step of 480MHz has been added on SKUs that have a RPL-U
> device id. Add a new table which include this new CDCLK step.
>
> BSpec: 55409
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.bo...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 39 ++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 0c107a38f9d0..9bfeb1abba47 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -180,6 +180,18 @@ static void i85x_get_cdclk(struct drm_i915_private
> *dev_priv,
> }
> }
>
> +static bool is_rplu(struct drm_i915_private *dev_priv)
> +{
> + switch (INTEL_DEVID(dev_priv)) {
> + case 0xA7A1:
> + case 0xA721:
> + case 0xA7A9:
No. Under no circumstances are you to sprinkle PCI ID checks directly in
code like this.
The only place where PCI IDs go are the macros in
include/drm/i915_pciids.h, and each PCI ID should be present there only
once.
Those macros should only be used in i915_pci.c and intel_device_info.c.
If you need a distinction between RPL-P and RPL-U like this (and I
didn't check this in the spec, just commenting on the implementation)
you need to split RPL-P and RPL-U definitions and add them as
subplatforms in intel_device_info.c.
As a general tip, when you consider using a function or a macro, look up
where it's used and how. INTEL_DEVID() isn't used like this anywhere.
BR,
Jani.
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
> struct intel_cdclk_config *cdclk_config)
> {
> @@ -1329,6 +1341,27 @@ static const struct intel_cdclk_vals
> adlp_cdclk_table[] = {
> {}
> };
>
> +static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> + { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> + { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> + { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> + { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> + { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> +
> + { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> + { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> + { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> + { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> + { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> +
> + { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> + {}
> +};
> +
> static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34,
> .waveform = 0x8888 },
> { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34,
> .waveform = 0x9248 },
> @@ -3353,6 +3386,12 @@ void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv)
> /* Wa_22011320316:adl-p[a0] */
> if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
> + /*
> + * BSpec: 55409
> + * 480 MHz supported on SKUs that have a RPL-U Device ID
> + */
> + else if (is_rplu(dev_priv))
> + dev_priv->cdclk.table = rplu_cdclk_table;
> else
> dev_priv->display.cdclk.table = adlp_cdclk_table;
> } else if (IS_ROCKETLAKE(dev_priv)) {
--
Jani Nikula, Intel Open Source Graphics Center
